cpu/intel/haswell: Allow use of TSC for the monotonic timer
When the Haswell-specific monotonic timer is used on an ASRock H81M-HDS with a Pentium G3258, the following exception is generated, causing the system to hang. CPU Index 0 - APIC 0 Unexpected Exception:13 @ 10:7f7a3736 - Halting Code: 0 eflags: 00010006 cr2: 00000000 eax: 00262626 ebx: 00140000 ecx: 00000603 edx: 00360000 edi: 00000007 esi: 00262626 ebp: 7f7c0fd8 esp: 7f7c0e90 The exception occurs when trying to read `MSR_COUNTER_24_MHz`, located at 0x637. This MSR only exists on Haswell-ULT CPUs. So, allow boards to use the TSC monotonic timer instead. They can do this by placing `select TSC_MONOTONIC_TIMER` in the mainboard Kconfig. Change-Id: I31d0e801b8cc85330dcb70c3fc03670f2e677e8f Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/29383 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -7,14 +7,17 @@ romstage-y += ../car/romstage.c
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ramstage-y += acpi.c
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ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
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ramstage-y += monotonic_timer.c
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romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
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postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
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ifneq ($(CONFIG_TSC_MONOTONIC_TIMER),y)
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ramstage-y += monotonic_timer.c
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smm-y += monotonic_timer.c
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endif
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cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
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postcar-y += ../car/non-evict/exit_car.S
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