intel/apollolake/spi: Add support for reading status reg
spi_read_status reads the status register using hardware sequencing and returns 0 on success and -1 on error. Use spi_read_status to return appropriate value for get_sw_write_protect. BUG=chrome-os-partner:54283 Change-Id: I7650b5c0ab05a8429c2b291f00d4672446d86e03 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15266 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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4 changed files with 31 additions and 0 deletions
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@ -30,6 +30,7 @@ romstage-y += mmap_boot.c
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romstage-y += tsc_freq.c
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romstage-y += tsc_freq.c
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romstage-y += pmutil.c
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romstage-y += pmutil.c
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romstage-y += reset.c
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romstage-y += reset.c
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romstage-y += spi.c
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smm-y += mmap_boot.c
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smm-y += mmap_boot.c
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smm-y += pmutil.c
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smm-y += pmutil.c
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@ -59,6 +59,7 @@
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#define SPIBAR_HSFSTS_CYCLE_WRITE SPIBAR_HSFSTS_FCYCLE(2)
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#define SPIBAR_HSFSTS_CYCLE_WRITE SPIBAR_HSFSTS_FCYCLE(2)
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#define SPIBAR_HSFSTS_CYCLE_4K_ERASE SPIBAR_HSFSTS_FCYCLE(3)
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#define SPIBAR_HSFSTS_CYCLE_4K_ERASE SPIBAR_HSFSTS_FCYCLE(3)
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#define SPIBAR_HSFSTS_CYCLE_64K_ERASE SPIBAR_HSFSTS_FCYCLE(4)
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#define SPIBAR_HSFSTS_CYCLE_64K_ERASE SPIBAR_HSFSTS_FCYCLE(4)
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#define SPIBAR_HSFSTS_CYCLE_RD_STATUS SPIBAR_HSFSTS_FCYCLE(8)
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/* Bit definitions for PTINX register */
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/* Bit definitions for PTINX register */
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#define SPIBAR_PTINX_COMP_0 (0 << 14)
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#define SPIBAR_PTINX_COMP_0 (0 << 14)
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@ -68,4 +69,10 @@
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#define SPIBAR_PTINX_HORD_JEDEC (2 << 12)
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#define SPIBAR_PTINX_HORD_JEDEC (2 << 12)
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#define SPIBAR_PTINX_IDX_MASK 0xffc
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#define SPIBAR_PTINX_IDX_MASK 0xffc
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/*
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* Reads status register. On success returns 0 and status contains the value
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* read from the status register. On error returns -1.
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*/
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int spi_read_status(uint8_t *status);
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#endif
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#endif
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@ -21,6 +21,7 @@
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#include <arch/io.h>
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#include <arch/io.h>
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#include <arch/symbols.h>
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#include <arch/symbols.h>
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#include <assert.h>
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#include <assert.h>
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#include <bootmode.h>
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#include <cbfs.h>
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#include <cbfs.h>
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#include <cbmem.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <console/console.h>
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@ -37,6 +38,7 @@
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#include <soc/pci_devs.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <soc/pm.h>
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#include <soc/romstage.h>
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#include <soc/romstage.h>
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#include <soc/spi.h>
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#include <soc/uart.h>
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#include <soc/uart.h>
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#include <string.h>
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#include <string.h>
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#include <timestamp.h>
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#include <timestamp.h>
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@ -260,3 +262,11 @@ void mainboard_memory_init_params(struct FSPM_UPD *mupd)
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{
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{
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printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
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printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
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}
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}
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int get_sw_write_protect_state(void)
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{
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uint8_t status;
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/* Return unprotected status if status read fails. */
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return spi_read_status(&status) ? 0 : !!(status & 0x80);
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}
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@ -373,3 +373,16 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
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return slave;
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return slave;
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}
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}
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int spi_read_status(uint8_t *status)
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{
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BOILERPLATE_CREATE_CTX(ctx);
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if (exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_RD_STATUS, 0,
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sizeof(*status)) != SUCCESS)
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return -1;
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drain_xfer_fifo(ctx, status, sizeof(*status));
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return 0;
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}
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