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Boards w/ Winbond superios: Use common config entry code 

Six mainboards with Winbond superios directly configure
them in romstage.c. All use the common Winbond romstage
code. Change them to use the common config entry code to
allow for code refactoring such as [1]. Build tested.

[1] https://review.coreboot.org/20988

Change-Id: Icecd52ec622b9da86edb07c52893f4db001e5562
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Keith Hui 2017-08-13 16:31:18 -04:00 committed by Martin Roth
parent 928c6c6336
commit bb73c98d24
6 changed files with 20 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/mainboard/asus/a8v-e_deluxe/romstage.c
View File

@ -94,7 +94,7 @@ static void sio_init(void)
{ {
u8 reg; u8 reg;
pnp_enter_ext_func_mode(SERIAL_DEV); pnp_enter_conf_state(SERIAL_DEV);
/* We have 24MHz input. */ /* We have 24MHz input. */
reg = pnp_read_config(SERIAL_DEV, 0x24); reg = pnp_read_config(SERIAL_DEV, 0x24);
pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));
@ -104,9 +104,9 @@ static void sio_init(void)
/* We have all RESTOUT and even some reserved bits, too. */ /* We have all RESTOUT and even some reserved bits, too. */
reg = pnp_read_config(SERIAL_DEV, 0x2c); reg = pnp_read_config(SERIAL_DEV, 0x2c);
pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0));
pnp_exit_ext_func_mode(SERIAL_DEV); pnp_exit_conf_state(SERIAL_DEV);
pnp_enter_ext_func_mode(ACPI_DEV); pnp_enter_conf_state(ACPI_DEV);
pnp_set_logical_device(ACPI_DEV); pnp_set_logical_device(ACPI_DEV);
/* /*
* Set the delay rising time from PWROK_LP to PWROK_ST to * Set the delay rising time from PWROK_LP to PWROK_ST to
@ -117,9 +117,9 @@ static void sio_init(void)
/* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */
reg = pnp_read_config(ACPI_DEV, 0xe4); reg = pnp_read_config(ACPI_DEV, 0xe4);
pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10));
pnp_exit_ext_func_mode(ACPI_DEV); pnp_exit_conf_state(ACPI_DEV);
pnp_enter_ext_func_mode(GPIO_DEV); pnp_enter_conf_state(GPIO_DEV);
pnp_set_logical_device(GPIO_DEV); pnp_set_logical_device(GPIO_DEV);
/* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */
pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */
@ -129,7 +129,7 @@ static void sio_init(void)
pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0 = output 1 = input */ pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0 = output 1 = input */
pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */
pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */
pnp_exit_ext_func_mode(GPIO_DEV); pnp_exit_conf_state(GPIO_DEV);
} }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

12
src/mainboard/asus/a8v-e_se/romstage.c
View File

@ -94,7 +94,7 @@ static void sio_init(void)
{ {
u8 reg; u8 reg;
pnp_enter_ext_func_mode(SERIAL_DEV); pnp_enter_conf_state(SERIAL_DEV);
/* We have 24MHz input. */ /* We have 24MHz input. */
reg = pnp_read_config(SERIAL_DEV, 0x24); reg = pnp_read_config(SERIAL_DEV, 0x24);
pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));
@ -104,9 +104,9 @@ static void sio_init(void)
/* We have all RESTOUT and even some reserved bits, too. */ /* We have all RESTOUT and even some reserved bits, too. */
reg = pnp_read_config(SERIAL_DEV, 0x2c); reg = pnp_read_config(SERIAL_DEV, 0x2c);
pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0));
pnp_exit_ext_func_mode(SERIAL_DEV); pnp_exit_conf_state(SERIAL_DEV);
pnp_enter_ext_func_mode(ACPI_DEV); pnp_enter_conf_state(ACPI_DEV);
pnp_set_logical_device(ACPI_DEV); pnp_set_logical_device(ACPI_DEV);
/* /*
* Set the delay rising time from PWROK_LP to PWROK_ST to * Set the delay rising time from PWROK_LP to PWROK_ST to
@ -117,9 +117,9 @@ static void sio_init(void)
/* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */
reg = pnp_read_config(ACPI_DEV, 0xe4); reg = pnp_read_config(ACPI_DEV, 0xe4);
pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10));
pnp_exit_ext_func_mode(ACPI_DEV); pnp_exit_conf_state(ACPI_DEV);
pnp_enter_ext_func_mode(GPIO_DEV); pnp_enter_conf_state(GPIO_DEV);
pnp_set_logical_device(GPIO_DEV); pnp_set_logical_device(GPIO_DEV);
/* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */
pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */
@ -129,7 +129,7 @@ static void sio_init(void)
pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0 = output 1 = input */ pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0 = output 1 = input */
pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */
pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */
pnp_exit_ext_func_mode(GPIO_DEV); pnp_exit_conf_state(GPIO_DEV);
} }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

4
src/mainboard/ibase/mb899/romstage.c
View File

@ -62,7 +62,7 @@ static void early_superio_config_w83627ehg(void)
pnp_devfn_t dev; pnp_devfn_t dev;
dev = DUMMY_DEV; dev = DUMMY_DEV;
pnp_enter_ext_func_mode(dev); pnp_enter_conf_state(dev);
pnp_write_config(dev, 0x24, 0xc4); // PNPCSV pnp_write_config(dev, 0x24, 0xc4); // PNPCSV
@ -121,7 +121,7 @@ static void early_superio_config_w83627ehg(void)
pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);
pnp_set_enable(dev, 1); pnp_set_enable(dev, 1);
pnp_exit_ext_func_mode(dev); pnp_exit_conf_state(dev);
} }
static void rcba_config(void) static void rcba_config(void)

4
src/mainboard/msi/ms7260/romstage.c
View File

@ -126,11 +126,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
/* FIXME: This should be part of the Super I/O code/config. */ /* FIXME: This should be part of the Super I/O code/config. */
pnp_enter_ext_func_mode(SERIAL_DEV); pnp_enter_conf_state(SERIAL_DEV);
/* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */ /* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */
pnp_write_config(SERIAL_DEV, 0x24, 0); pnp_write_config(SERIAL_DEV, 0x24, 0);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV); pnp_exit_conf_state(SERIAL_DEV);
setup_mb_resource_map(); setup_mb_resource_map();
console_init(); console_init();

4
src/mainboard/msi/ms9652_fam10/romstage.c
View File

@ -129,11 +129,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x32); post_code(0x32);
pnp_enter_ext_func_mode(SERIAL_DEV); pnp_enter_conf_state(SERIAL_DEV);
/* We have 24MHz input. */ /* We have 24MHz input. */
reg = pnp_read_config(SERIAL_DEV, 0x24); reg = pnp_read_config(SERIAL_DEV, 0x24);
pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf)); pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf));
pnp_exit_ext_func_mode(SERIAL_DEV); pnp_exit_conf_state(SERIAL_DEV);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();

4
src/mainboard/nvidia/l1_2pvv/romstage.c
View File

@ -124,9 +124,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (bist == 0) if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
pnp_enter_ext_func_mode(SERIAL_DEV); pnp_enter_conf_state(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x24, 0); pnp_write_config(SERIAL_DEV, 0x24, 0);
pnp_exit_ext_func_mode(SERIAL_DEV); pnp_exit_conf_state(SERIAL_DEV);
setup_mb_resource_map(); setup_mb_resource_map();