nb/intel/x4x: Define and use MMCONF_BUS_NUMBER
Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR register. The `length` bitfield was set to 0, so assume 256 busses. Moreover, the ASL reservation for MMCONFIG was only for 64 busses. Change-Id: I7366a5096aacd92401535be020358447650b4247 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49759 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Angel Pons
parent
1318ab475d
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bbc80f4405
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@ -25,6 +25,10 @@ config VGA_BIOS_ID
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config MMCONF_BASE_ADDRESS
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default 0xe0000000
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config MMCONF_BUS_NUMBER
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int
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default 256
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config SMM_RESERVED_SIZE
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hex
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default 0x100000
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@ -1,6 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <types.h>
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#include <console/console.h>
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#include <acpi/acpi.h>
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#include <acpi/acpigen.h>
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@ -9,13 +8,8 @@
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unsigned long acpi_fill_mcfg(unsigned long current)
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{
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u32 pciexbar, length;
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if (!decode_pcie_bar(&pciexbar, &length))
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return current;
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current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
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pciexbar, 0x0, 0x0, (length >> 20) - 1);
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current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
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CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1);
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return current;
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}
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@ -15,7 +15,7 @@ Device (PDRC)
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Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
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Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
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Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
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Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
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Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
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Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
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Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
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Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
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@ -2,15 +2,27 @@
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#include <arch/bootblock.h>
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#include <arch/mmio.h>
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#include <assert.h>
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#include <device/pci_ops.h>
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#include <types.h>
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#include "x4x.h"
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static uint32_t encode_pciexbar_length(void)
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{
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switch (CONFIG_MMCONF_BUS_NUMBER) {
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case 256: return 0 << 1;
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case 128: return 1 << 1;
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case 64: return 2 << 1;
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default: return dead_code_t(uint32_t);
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}
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}
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void bootblock_early_northbridge_init(void)
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{
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/* Disable LaGrande Technology (LT) */
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read32((void *)TPM_BASE_ADDRESS);
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const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | 16 | 1;
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const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
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pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32);
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}
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@ -57,42 +57,6 @@ u32 decode_tseg_size(const u32 esmramc)
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}
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}
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int decode_pcie_bar(u32 *const base, u32 *const len)
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{
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*base = 0;
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*len = 0;
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const struct {
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u16 num_buses;
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u32 addr_mask;
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} busmask[] = {
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{256, 0xf0000000},
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{128, 0xf8000000},
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{64, 0xfc000000},
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{0, 0},
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};
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const u32 pciexbar_reg = pci_read_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO);
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if (!(pciexbar_reg & 1)) {
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printk(BIOS_WARNING, "WARNING: MMCONF not set\n");
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return 0;
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}
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const u32 index = (pciexbar_reg >> 1) & 3;
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const u32 pciexbar = pciexbar_reg & busmask[index].addr_mask;
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const int max_buses = busmask[index].num_buses;
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if (!pciexbar) {
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printk(BIOS_WARNING, "WARNING: pciexbar invalid\n");
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return 0;
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}
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*base = pciexbar;
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*len = max_buses << 20;
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return 1;
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}
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static size_t northbridge_get_tseg_size(void)
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{
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const u8 esmramc = pci_read_config8(HOST_BRIDGE, D0F0_ESMRAMC);
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@ -20,7 +20,6 @@ static void mch_domain_read_resources(struct device *dev)
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u8 index;
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u64 tom, touud;
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u32 tomk, tolud, delta_cbmem;
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u32 pcie_config_base, pcie_config_size;
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u32 uma_sizek = 0;
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const u32 top32memk = 4 * (GiB / KiB);
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@ -111,12 +110,7 @@ static void mch_domain_read_resources(struct device *dev)
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top32memk - (DEFAULT_HECIBAR >> 10),
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IORESOURCE_RESERVE);
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if (decode_pcie_bar(&pcie_config_base, &pcie_config_size)) {
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printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
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"size=0x%x\n", pcie_config_base, pcie_config_size);
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fixed_mem_resource(dev, index++, pcie_config_base >> 10,
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pcie_config_size >> 10, IORESOURCE_RESERVE);
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}
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mmconf_resource(dev, index++);
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}
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static void mch_domain_set_resources(struct device *dev)
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@ -172,7 +172,6 @@ void mb_pre_raminit_setup(int s3_resume);
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u32 decode_igd_memory_size(u32 gms);
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u32 decode_igd_gtt_size(u32 gsm);
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u32 decode_tseg_size(const u32 esmramc);
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int decode_pcie_bar(u32 *const base, u32 *const len);
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#include <device/device.h>
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struct acpi_rsdp;
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