soc/intel/common: Drop old forked version of SMBUS support
Switch to use the more recent version in sb/intel/common. Change-Id: Idbff410991db9592a58b9cc0ae7ee8c45d750b13 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Kyösti Mälkki
parent
d1c69c65ce
commit
bbcf1a0878
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@ -20,6 +20,7 @@
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <soc/smbus.h>
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#include <southbridge/intel/common/smbus.h>
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#include "smbuslib.h"
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static int lsmbus_read_byte(struct device *dev, u8 address)
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@ -13,171 +13,12 @@
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/smbus_def.h>
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#include <spd_bin.h>
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#include <southbridge/intel/common/smbus.h>
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#include <string.h>
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#include <timer.h>
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#include "smbuslib.h"
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static int smbus_wait_till_ready(u16 smbus_base)
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{
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struct stopwatch sw;
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unsigned char byte;
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stopwatch_init_msecs_expire(&sw, SMBUS_TIMEOUT);
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do {
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byte = inb(smbus_base + SMBHSTSTAT);
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if (!(byte & 1))
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return 0;
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} while (!stopwatch_expired(&sw));
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return -1;
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}
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static int smbus_wait_till_done(u16 smbus_base)
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{
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struct stopwatch sw;
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unsigned char byte;
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stopwatch_init_msecs_expire(&sw, SMBUS_TIMEOUT);
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do {
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byte = inb(smbus_base + SMBHSTSTAT);
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if (!((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0))
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return 0;
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} while (!stopwatch_expired(&sw));
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return -1;
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}
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int do_smbus_read_byte(unsigned int smbus_base, u8 device, unsigned int address)
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{
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unsigned char global_status_register;
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unsigned char byte;
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if (smbus_wait_till_ready(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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/* Setup transaction */
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/* Disable interrupts */
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outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
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/* Set the device I'm talking to */
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outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD);
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/* Set the command/address... */
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outb(address & 0xff, smbus_base + SMBHSTCMD);
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/* Set up for a byte data read */
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outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
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(smbus_base + SMBHSTCTL));
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/* Clear any lingering errors, so the transaction will run */
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outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
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/* Clear the data byte... */
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outb(0, smbus_base + SMBHSTDAT0);
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/* Start the command */
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outb((inb(smbus_base + SMBHSTCTL) | 0x40),
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smbus_base + SMBHSTCTL);
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/* Poll for transaction completion */
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if (smbus_wait_till_done(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
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global_status_register = inb(smbus_base + SMBHSTSTAT);
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/* Ignore the "In Use" status... */
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global_status_register &= ~(3 << 5);
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/* Read results of transaction */
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byte = inb(smbus_base + SMBHSTDAT0);
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if (global_status_register != (1 << 1))
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return SMBUS_ERROR;
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return byte;
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}
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int do_smbus_write_byte(unsigned int smbus_base, u8 device, unsigned int address,
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unsigned int data)
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{
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unsigned char global_status_register;
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if (smbus_wait_till_ready(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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/* Setup transaction */
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/* Disable interrupts */
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outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
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/* Set the device I'm talking to */
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outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
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/* Set the command/address... */
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outb(address & 0xff, smbus_base + SMBHSTCMD);
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/* Set up for a byte data read */
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outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
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(smbus_base + SMBHSTCTL));
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/* Clear any lingering errors, so the transaction will run */
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outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
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/* Clear the data byte... */
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outb(data, smbus_base + SMBHSTDAT0);
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/* Start the command */
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outb((inb(smbus_base + SMBHSTCTL) | 0x40),
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smbus_base + SMBHSTCTL);
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/* Poll for transaction completion */
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if (smbus_wait_till_done(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
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global_status_register = inb(smbus_base + SMBHSTSTAT);
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/* Ignore the "In Use" status... */
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global_status_register &= ~(3 << 5);
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/* Read results of transaction */
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if (global_status_register != (1 << 1))
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return SMBUS_ERROR;
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return 0;
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}
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int do_smbus_read_word(unsigned int smbus_base, u8 device, unsigned int address)
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{
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unsigned char global_status_register;
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unsigned short data;
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if (smbus_wait_till_ready(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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/* Set up transaction */
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/* Disable interrupts */
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outb(inb(smbus_base + SMBHSTCTL) & ~1, smbus_base + SMBHSTCTL);
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/* Set the device I'm talking to */
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outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD);
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/* Set the command/address... */
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outb(address & 0xff, smbus_base + SMBHSTCMD);
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/* Set up for a word data read */
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outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x3 << 2),
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(smbus_base + SMBHSTCTL));
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/* Clear any lingering errors, so the transaction will run */
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outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
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/* Start the command */
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outb((inb(smbus_base + SMBHSTCTL) | 0x40),
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smbus_base + SMBHSTCTL);
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/* Poll for transaction completion */
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if (smbus_wait_till_done(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
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global_status_register = inb(smbus_base + SMBHSTSTAT);
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/* Ignore the "In Use" status... */
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if ((global_status_register & ~(3 << 5)) != (1 << 1))
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return SMBUS_ERROR;
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/* Read results of transaction */
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data = inw(smbus_base + SMBHSTDAT0);
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return data;
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}
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static void update_spd_len(struct spd_block *blk)
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{
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u8 i, j = 0;
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@ -20,6 +20,7 @@
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/* SMBus IO Base Address */
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#define SMBUS_IO_BASE 0xefa0
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/* PCI Configuration Space : SMBus */
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#define HOSTC 0x40
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#define HST_EN (1 << 0)
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@ -32,9 +33,4 @@
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#define SMBUS_TIMEOUT 15 /* 15ms */
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int do_smbus_read_byte(unsigned int smbus_base, u8 device, unsigned int address);
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int do_smbus_write_byte(unsigned int smbus_base, u8 device, unsigned int address,
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unsigned int data);
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int do_smbus_read_word(unsigned int smbus_base, u8 device, unsigned int address);
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#endif /* SOC_INTEL_COMMON_BLOCK_SMBUS__LIB_H */
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@ -44,5 +44,6 @@ config PCH_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_XDCI
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select SOC_INTEL_COMMON_BLOCK_XHCI
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select SOC_INTEL_COMMON_PCH_LOCKDOWN
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select SOUTHBRIDGE_INTEL_COMMON_SMBUS
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endif
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