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soc/intel/*: Allow configuring 8254 timer via CMOS 

Currently, the `USE_LEGACY_8254_TIMER` Kconfig option is the only way
to enable or disable the legacy 8254 timer. Add the `legacy_8254_timer`
CMOS option to allow enabling and disabling the 8254 timer without
having to rebuild and reflash coreboot. If options are not enabled or
the option is missing in cmos.layout, the Kconfig setting is used.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic82c7f25cdf6587de5c40f59441579cfc92ff2f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Sean Rhodes 2021-07-13 13:36:28 +01:00 committed by Paul Fagerburg
parent c0308eb860
commit bc35bed18e
7 changed files with 32 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/soc/intel/alderlake/fsp_params.c
View File

@ -8,6 +8,7 @@
#include <fsp/api.h>
#include <fsp/ppi/mp_service_ppi.h>
#include <fsp/util.h>
#include <option.h>
#include <intelblocks/irq.h>
#include <intelblocks/lpss.h>
#include <intelblocks/xdci.h>
@ -21,6 +22,7 @@
#include <soc/soc_chip.h>
#include <stdlib.h>
#include <string.h>
#include <types.h>
/* THC assignment definition */
#define THC_NONE 0
@ -533,8 +535,9 @@ static void fill_fsps_8254_params(FSP_S_CONFIG *s_cfg,
const struct soc_intel_alderlake_config *config)
{
/* Legacy 8254 timer support */
s_cfg->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);
s_cfg->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER);
bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER));
s_cfg->Enable8254ClockGating = !use_8254;
s_cfg->Enable8254ClockGatingOnS3 = !use_8254;
}
static void fill_fsps_storage_params(FSP_S_CONFIG *s_cfg,

7
src/soc/intel/cannonlake/fsp_params.c
View File

@ -7,6 +7,7 @@
#include <device/pci.h>
#include <fsp/api.h>
#include <fsp/util.h>
#include <option.h>
#include <intelblocks/irq.h>
#include <intelblocks/lpss.h>
#include <intelblocks/power_limit.h>
@ -17,6 +18,7 @@
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <string.h>
#include <types.h>
#include "chip.h"
@ -425,8 +427,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
/* Legacy 8254 timer support */
params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);
params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER);
bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER));
params->Enable8254ClockGating = !use_8254;
params->Enable8254ClockGatingOnS3 = !use_8254;
params->EnableTcoTimer = CONFIG(USE_PM_ACPI_TIMER);

5
src/soc/intel/elkhartlake/fsp_params.c
View File

@ -5,6 +5,7 @@
#include <fsp/api.h>
#include <fsp/ppi/mp_service_ppi.h>
#include <fsp/util.h>
#include <option.h>
#include <intelblocks/lpss.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/xdci.h>
@ -14,6 +15,7 @@
#include <soc/ramstage.h>
#include <soc/soc_chip.h>
#include <string.h>
#include <types.h>
/* SATA DEVSLP idle timeout default values */
#define DEF_DMVAL 15
@ -159,7 +161,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PavpEnable = 0;
/* Legacy 8254 timer support */
params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);
bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER));
params->Enable8254ClockGating = !use_8254;
params->Enable8254ClockGatingOnS3 = 1;
/* PCH Master Gating Control */

7
src/soc/intel/icelake/fsp_params.c
View File

@ -5,6 +5,7 @@
#include <device/pci.h>
#include <fsp/api.h>
#include <fsp/util.h>
#include <option.h>
#include <intelblocks/lpss.h>
#include <intelblocks/xdci.h>
#include <soc/intel/common/vbt.h>
@ -12,6 +13,7 @@
#include <soc/ramstage.h>
#include <soc/soc_chip.h>
#include <string.h>
#include <types.h>
#include <fsp/ppi/mp_service_ppi.h>
static void parse_devicetree(FSP_S_CONFIG *params)
@ -92,8 +94,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
/* Legacy 8254 timer support */
params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);
params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER);
bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER));
params->Enable8254ClockGating = !use_8254;
params->Enable8254ClockGatingOnS3 = !use_8254;
/* S0ix */
params->PchPmSlpS0Enable = config->s0ix_enable;

5
src/soc/intel/jasperlake/fsp_params.c
View File

@ -5,6 +5,7 @@
#include <fsp/api.h>
#include <fsp/ppi/mp_service_ppi.h>
#include <fsp/util.h>
#include <option.h>
#include <intelblocks/lpss.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/xdci.h>
@ -14,6 +15,7 @@
#include <soc/ramstage.h>
#include <soc/soc_chip.h>
#include <string.h>
#include <types.h>
/*
* ME End of Post configuration
@ -84,7 +86,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->EndOfPostMessage = EOP_DISABLE;
/* Legacy 8254 timer support */
params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);
bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER));
params->Enable8254ClockGating = !use_8254;
params->Enable8254ClockGatingOnS3 = 1;
/* disable Legacy PME */

5
src/soc/intel/skylake/chip.c
View File

@ -9,6 +9,7 @@
#include <device/pci_ids.h>
#include <fsp/util.h>
#include <gpio.h>
#include <option.h>
#include <intelblocks/cfg.h>
#include <intelblocks/itss.h>
#include <intelblocks/lpc_lib.h>
@ -28,6 +29,7 @@
#include <soc/systemagent.h>
#include <soc/usb.h>
#include <string.h>
#include <types.h>
#include "chip.h"
@ -340,7 +342,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
/* Legacy 8254 timer support */
params->Early8254ClockGatingEnable = !CONFIG(USE_LEGACY_8254_TIMER);
bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER));
params->Early8254ClockGatingEnable = !use_8254;
params->EnableTcoTimer = CONFIG(USE_PM_ACPI_TIMER);

7
src/soc/intel/tigerlake/fsp_params.c
View File

@ -11,6 +11,7 @@
#include <fsp/api.h>
#include <fsp/ppi/mp_service_ppi.h>
#include <fsp/util.h>
#include <option.h>
#include <intelblocks/cse.h>
#include <intelblocks/irq.h>
#include <intelblocks/lpss.h>
@ -26,6 +27,7 @@
#include <soc/soc_chip.h>
#include <soc/tcss.h>
#include <string.h>
#include <types.h>
/* THC assignment definition */
#define THC_NONE 0
@ -547,8 +549,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->ThcPort1Assignment = is_devfn_enabled(PCH_DEVFN_THC1) ? THC_1 : THC_NONE;
/* Legacy 8254 timer support */
params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);
params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER);
bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER));
params->Enable8254ClockGating = !use_8254;
params->Enable8254ClockGatingOnS3 = !use_8254;
/* Enable Hybrid storage auto detection */
if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && cse_is_hfs3_fw_sku_lite()