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google/lars: Enable SaGv feature 

This change enables SaGv feature for skylake
platform. As a result of this patch the skylake
platform will train memory at both low & high
frequency points. This will be used to
dynamically scale the work point
(voltage/frequencies).

The value "3" here means enable. Following
is the table for same.

0=Disabled (SaGv disabled)
1=FixedLow (Fixed to low frequency)
2=FixedHigh (Fixed to High frequency)
3=Enabled( SaGv Enabled.Dynamically changes)

BRANCH=None
BUG=chrome-os-partner:48534
TEST=Build and boot lars

Change-Id: I82b1a428d2d3dce47f46de576f677cf2249b6b5d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8e252123cc73543d0f1b320af9d8873f99a45ab1
Original-Change-Id: I1a545ff2f38df23964378c0d833e29006b2c5557
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/320022
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Reviewed-on: https://review.coreboot.org/13002
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
david 2015-12-28 20:28:58 +08:00 committed by Patrick Georgi
parent 07e9e6f737
commit bc58a878cd
1 changed files with 1 additions and 0 deletions
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1
src/mainboard/google/lars/devicetree.cb
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@ -30,6 +30,7 @@ chip soc/intel/skylake
register "SkipExtGfxScan" = "1" register "SkipExtGfxScan" = "1"
register "Device4Enable" = "1" register "Device4Enable" = "1"
register "HeciEnabled" = "0" register "HeciEnabled" = "0"
register "SaGv" = "3"
register "FspSkipMpInit" = "1" register "FspSkipMpInit" = "1"
# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch