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soc/intel/alderlake/bootblock/pch.c: Enable SIO 4e/4f ports decoding 

Some Super I/Os may be strapped to respond on the secondary ports
0x4e/0x4f. Enable them early so that mainboard is able to initialize
a serial port for example.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I6df158f54a48fb9f3173a4b209316c8116aa265a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Michał Żygowski 2022-04-07 15:10:35 +02:00
parent dccfb8a215
commit bc749a068a
1 changed files with 2 additions and 2 deletions
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4
src/soc/intel/alderlake/bootblock/pch.c
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@ -103,8 +103,8 @@ static void soc_config_acpibase(void)
void pch_early_iorange_init(void)
{
uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
LPC_IOE_EC_62_66 | LPC_IOE_LGE_200;
uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_EC_4E_4F |
LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66 | LPC_IOE_LGE_200;
/* IO Decode Range */
if (CONFIG(DRIVERS_UART_8250IO))