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Fix i945 based boards 

- prevent GCC from inlining do_ram_command - it will break RAM initialization.
- fix the PCIRST# mechanism in those boards that do it, it requires 200ms, not 
  200us
- move PCIRST# as early as possible (before ich7_enable_lpc)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2010-08-25 18:35:42 +00:00 committed by Stefan Reinauer
parent 6f22ecc2c9
commit bc8613ecaf
4 changed files with 7 additions and 9 deletions
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3
src/mainboard/getac/p470/romstage.c
View File

@ -308,9 +308,8 @@ void main(unsigned long bist)
#if 0 #if 0
/* Force PCIRST# */ /* Force PCIRST# */
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
udelay(200); udelay(200 * 1000);
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
udelay(200);
#endif #endif
ich7_enable_lpc(); ich7_enable_lpc();

6
src/mainboard/kontron/986lcd-m/romstage.c
View File

@ -366,14 +366,12 @@ void main(unsigned long bist)
enable_lapic(); enable_lapic();
} }
ich7_enable_lpc();
/* Force PCIRST# */ /* Force PCIRST# */
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
udelay(200); udelay(200 * 1000);
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
udelay(200);
ich7_enable_lpc();
early_superio_config_w83627thg(); early_superio_config_w83627thg();
/* Set up the console */ /* Set up the console */

5
src/mainboard/roda/rk886ex/romstage.c
View File

@ -279,11 +279,12 @@ void main(unsigned long bist)
enable_lapic(); enable_lapic();
} }
ich7_enable_lpc();
/* Force PCIRST# */ /* Force PCIRST# */
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
udelay(200 * 1000);
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
ich7_enable_lpc();
early_superio_config(); early_superio_config();
/* Set up the console */ /* Set up the console */

2
src/northbridge/intel/i945/raminit.c
View File

@ -45,7 +45,7 @@
#define RAM_EMRS_2 (0x1 << 21) #define RAM_EMRS_2 (0x1 << 21)
#define RAM_EMRS_3 (0x2 << 21) #define RAM_EMRS_3 (0x2 << 21)
static void do_ram_command(u32 command) static __attribute__((noinline)) void do_ram_command(u32 command)
{ {
u32 reg32; u32 reg32;