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soc/amd/picasso: make USB over-current pin mapping configurable 

Neither the family 17h model 10-1Fh PPR nor the internal FSP source
seems to have the mapping of the USB OC pins to the four bit values, so
this is based on the information from the family 15h model 70-7Fh BKDG
which also corresponds to what I'd have expected here.

BUG=b:162010077

Change-Id: I581ef1d730e9d729d9849d7e73ef1c1b67b2c4cf
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Felix Held 2020-07-24 19:10:03 +02:00
parent 1e5edb48c3
commit bcb3d03973
2 changed files with 21 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/soc/amd/picasso/chip.h
View File

@ -137,6 +137,15 @@ struct soc_amd_picasso_config {
uint8_t has_usb2_phy_tune_params; uint8_t has_usb2_phy_tune_params;
struct usb2_phy_tune usb_2_port_tune_params[USB_PORT_COUNT]; struct usb2_phy_tune usb_2_port_tune_params[USB_PORT_COUNT];
enum {
USB_OC_PIN_0 = 0x0,
USB_OC_PIN_1 = 0x1,
USB_OC_PIN_2 = 0x2,
USB_OC_PIN_3 = 0x3,
USB_OC_PIN_4 = 0x4,
USB_OC_PIN_5 = 0x5,
USB_OC_NONE = 0xf,
} usb_port_overcurrent_pin[USB_PORT_COUNT];
}; };
typedef struct soc_amd_picasso_config config_t; typedef struct soc_amd_picasso_config config_t;

13
src/soc/amd/picasso/fsp_params.c
View File

@ -98,17 +98,28 @@ static void fsp_fill_pcie_ddi_descriptors(FSP_S_CONFIG *scfg)
static void fsp_usb_oem_customization(FSP_S_CONFIG *scfg, static void fsp_usb_oem_customization(FSP_S_CONFIG *scfg,
const struct soc_amd_picasso_config *cfg) const struct soc_amd_picasso_config *cfg)
{ {
size_t i;
ASSERT(FSPS_UPD_USB2_PORT_COUNT == USB_PORT_COUNT); ASSERT(FSPS_UPD_USB2_PORT_COUNT == USB_PORT_COUNT);
/* each OC mapping in xhci_oc_pin_select is 4 bit per USB port */
ASSERT(2 * sizeof(scfg->xhci_oc_pin_select) >= USB_PORT_COUNT);
scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1; scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1;
if (cfg->has_usb2_phy_tune_params) { if (cfg->has_usb2_phy_tune_params) {
for (size_t i = 0; i < FSPS_UPD_USB2_PORT_COUNT; i++) { for (i = 0; i < FSPS_UPD_USB2_PORT_COUNT; i++) {
memcpy(scfg->fch_usb_2_port_phy_tune[i], memcpy(scfg->fch_usb_2_port_phy_tune[i],
&cfg->usb_2_port_tune_params[i], &cfg->usb_2_port_tune_params[i],
sizeof(scfg->fch_usb_2_port_phy_tune[0])); sizeof(scfg->fch_usb_2_port_phy_tune[0]));
} }
} }
/* lowest nibble of xhci_oc_pin_select corresponds to OC mapping of first USB port */
for (i = 0; i < USB_PORT_COUNT; i++) {
scfg->xhci_oc_pin_select &= ~(0xf << (i * 4));
scfg->xhci_oc_pin_select |=
(cfg->usb_port_overcurrent_pin[i] & 0xf) << (i * 4);
}
} }
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)