soc/amd/picasso: make USB over-current pin mapping configurable
Neither the family 17h model 10-1Fh PPR nor the internal FSP source seems to have the mapping of the USB OC pins to the four bit values, so this is based on the information from the family 15h model 70-7Fh BKDG which also corresponds to what I'd have expected here. BUG=b:162010077 Change-Id: I581ef1d730e9d729d9849d7e73ef1c1b67b2c4cf Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -137,6 +137,15 @@ struct soc_amd_picasso_config {
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uint8_t has_usb2_phy_tune_params;
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struct usb2_phy_tune usb_2_port_tune_params[USB_PORT_COUNT];
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enum {
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USB_OC_PIN_0 = 0x0,
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USB_OC_PIN_1 = 0x1,
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USB_OC_PIN_2 = 0x2,
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USB_OC_PIN_3 = 0x3,
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USB_OC_PIN_4 = 0x4,
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USB_OC_PIN_5 = 0x5,
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USB_OC_NONE = 0xf,
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} usb_port_overcurrent_pin[USB_PORT_COUNT];
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};
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typedef struct soc_amd_picasso_config config_t;
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@ -98,17 +98,28 @@ static void fsp_fill_pcie_ddi_descriptors(FSP_S_CONFIG *scfg)
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static void fsp_usb_oem_customization(FSP_S_CONFIG *scfg,
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const struct soc_amd_picasso_config *cfg)
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{
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size_t i;
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ASSERT(FSPS_UPD_USB2_PORT_COUNT == USB_PORT_COUNT);
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/* each OC mapping in xhci_oc_pin_select is 4 bit per USB port */
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ASSERT(2 * sizeof(scfg->xhci_oc_pin_select) >= USB_PORT_COUNT);
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scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1;
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if (cfg->has_usb2_phy_tune_params) {
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for (size_t i = 0; i < FSPS_UPD_USB2_PORT_COUNT; i++) {
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for (i = 0; i < FSPS_UPD_USB2_PORT_COUNT; i++) {
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memcpy(scfg->fch_usb_2_port_phy_tune[i],
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&cfg->usb_2_port_tune_params[i],
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sizeof(scfg->fch_usb_2_port_phy_tune[0]));
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}
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}
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/* lowest nibble of xhci_oc_pin_select corresponds to OC mapping of first USB port */
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for (i = 0; i < USB_PORT_COUNT; i++) {
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scfg->xhci_oc_pin_select &= ~(0xf << (i * 4));
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scfg->xhci_oc_pin_select |=
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(cfg->usb_port_overcurrent_pin[i] & 0xf) << (i * 4);
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}
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}
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void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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