intel/i945,gm45,pineview,x4x: Fix stage cache location

The cache is at the end of TSEG. As SMM_RESERVED_SIZE was
half of TSEG size, offseting from the start gave same
position.

Change-Id: I2d5df90b40ff7cd9fde3cbe3cc5090aac74825f7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/northbridge/intel/gm45/ram_calc.c

@@ -126,13 +126,12 @@ void *cbmem_top(void)
 
 void stage_cache_external_region(void **base, size_t *size)
 {
-	/*
+	/* The stage cache lives at the end of the TSEG region.
-	 * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
 	 * The top of RAM is defined to be the TSEG base address.
 	 */
 	*size = CONFIG_SMM_RESERVED_SIZE;
-	*base = (void *)(northbridge_get_tseg_base()
+	*base = (void *)((uintptr_t)northbridge_get_tseg_base()
-			 + CONFIG_SMM_RESERVED_SIZE);
+		+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
 }
 
 /* platform_enter_postcar() determines the stack to use after

src/northbridge/intel/i945/ram_calc.c

@@ -92,13 +92,12 @@ u32 decode_igd_memory_size(const u32 gms)
 
 void stage_cache_external_region(void **base, size_t *size)
 {
-	/*
+	/* The stage cache lives at the end of the TSEG region.
-	 * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
 	 * The top of RAM is defined to be the TSEG base address.
 	 */
 	*size = CONFIG_SMM_RESERVED_SIZE;
-	*base = (void *)(northbridge_get_tseg_base()
+	*base = (void *)((uintptr_t)northbridge_get_tseg_base()
-			 + CONFIG_SMM_RESERVED_SIZE);
+		+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
 }
 
 /* platform_enter_postcar() determines the stack to use after

src/northbridge/intel/pineview/ram_calc.c

@@ -142,13 +142,12 @@ void *cbmem_top(void)
 
 void stage_cache_external_region(void **base, size_t *size)
 {
-	/*
+	/* The stage cache lives at the end of the TSEG region.
-	 * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
 	 * The top of RAM is defined to be the TSEG base address.
 	 */
 	*size = CONFIG_SMM_RESERVED_SIZE;
-	*base = (void *)(northbridge_get_tseg_base()
+	*base = (void *)((uintptr_t)northbridge_get_tseg_base()
-			 + CONFIG_SMM_RESERVED_SIZE);
+		+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
 }
 
 /* platform_enter_postcar() determines the stack to use after

src/northbridge/intel/x4x/ram_calc.c

@@ -137,13 +137,12 @@ void *cbmem_top(void)
 
 void stage_cache_external_region(void **base, size_t *size)
 {
-	/*
+	/* The stage cache lives at the end of the TSEG region.
-	 * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
 	 * The top of RAM is defined to be the TSEG base address.
 	 */
 	*size = CONFIG_SMM_RESERVED_SIZE;
-	*base = (void *)(northbridge_get_tseg_base()
+	*base = (void *)((uintptr_t)northbridge_get_tseg_base()
-			 + CONFIG_SMM_RESERVED_SIZE);
+		+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
 }
 
 /* platform_enter_postcar() determines the stack to use after