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mainboard/lenovo/t430s,t530,x230:enable usb3, set xhci overcurrent mapping 

Tested on T530, T430s.
Verified with lspci dump.

Change-Id: I45acadb0c55534a67f7ad3e7bd84f4482a4344d7
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/9451
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
This commit is contained in:
Nicolas Reinecke 2015-03-31 01:40:46 +02:00 committed by Edward O'Callaghan
parent 59aef5c79e
commit bcff3bd1b3
3 changed files with 9 additions and 0 deletions
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4
src/mainboard/lenovo/t430s/devicetree.cb
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@ -67,6 +67,10 @@ chip northbridge/intel/sandybridge
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
register "xhci_switchable_ports" = "0xf"
register "superspeed_capable_ports" = "0xf"
register "xhci_overcurrent_mapping" = "0x4000201"
# Enable zero-based linear PCIe root port functions # Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1" register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported register "c2_latency" = "101" # c2 not supported

4
src/mainboard/lenovo/t530/devicetree.cb
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@ -68,6 +68,10 @@ chip northbridge/intel/sandybridge
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
register "xhci_switchable_ports" = "0xf"
register "superspeed_capable_ports" = "0xf"
register "xhci_overcurrent_mapping" = "0x4000201"
device pci 14.0 on end # USB 3.0 Controller device pci 14.0 on end # USB 3.0 Controller
device pci 16.0 on end # Management Engine Interface 1 device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2 device pci 16.1 off end # Management Engine Interface 2

1
src/mainboard/lenovo/x230/devicetree.cb
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@ -69,6 +69,7 @@ chip northbridge/intel/sandybridge
register "xhci_switchable_ports" = "0xf" register "xhci_switchable_ports" = "0xf"
register "superspeed_capable_ports" = "0xf" register "superspeed_capable_ports" = "0xf"
register "xhci_overcurrent_mapping" = "0x4000201"
# Enable zero-based linear PCIe root port functions # Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1" register "pcie_port_coalesce" = "1"