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arch/riscv/ramstage.S: Add comments for passed arguments 

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ib1af1359249008d9eba351271637748a7edcec26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78966
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Maximilian Brune 2023-11-09 17:53:34 +01:00 committed by Lean Sheng Tan
parent 7698ebe162
commit bd06a297d5
1 changed files with 6 additions and 1 deletions
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7
src/arch/riscv/ramstage.S
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@ -7,7 +7,11 @@
.section ".text._start", "ax", %progbits
.globl _start
_start:
/* cbmem_top is passed via a2 */
# The romstage may pass the following arguments:
# a0: the value of mhartid
# a1: a pointer to the flattened devicetree
# a2: cbmem_top
la t0, _cbmem_top_ptr
#if __riscv_xlen == 32
sw a2, (t0)
@ -28,6 +32,7 @@ _start:
# initialize hart-local storage
csrr a0, mhartid
#NOTE a1 contains FDT and should not be cluttered above
call hls_init
li a0, CONFIG_RISCV_WORKING_HARTID