soc/intel/gma: Implement fsp_soc_get_igd_bar() in common code

`fsp/util.h` draws incompatible UDK headers in. Hence, we have to
declare it locally again.

Change-Id: Iaa5981088eeb5c36f765d6332ae47a38a6a4c875
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40729
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nico Huber 2020-04-26 20:43:42 +02:00
parent dd274e2971
commit bd4af105c4
12 changed files with 11 additions and 69 deletions

View File

@ -54,7 +54,6 @@ ramstage-y += cpu.c
ramstage-y += chip.c
ramstage-y += cse.c
ramstage-y += elog.c
ramstage-y += graphics.c
ramstage-y += gspi.c
ramstage-y += heci.c
ramstage-y += i2c.c

View File

@ -1,10 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <fsp/util.h>
#include <intelblocks/graphics.h>
#include <types.h>
uintptr_t fsp_soc_get_igd_bar(void)
{
return graphics_get_memory_base();
}

View File

@ -36,7 +36,6 @@ ramstage-y += cpu.c
ramstage-y += elog.c
ramstage-y += finalize.c
ramstage-y += fsp_params.c
ramstage-y += graphics.c
ramstage-y += gspi.c
ramstage-y += i2c.c
ramstage-y += lockdown.c

View File

@ -1,13 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <acpi/acpi.h>
#include <fsp/util.h>
#include <device/device.h>
#include <drivers/intel/gma/i915_reg.h>
#include <intelblocks/graphics.h>
#include <types.h>
uintptr_t fsp_soc_get_igd_bar(void)
{
return graphics_get_memory_base();
}

View File

@ -12,6 +12,7 @@
#include <drivers/intel/gma/opregion.h>
#include <intelblocks/graphics.h>
#include <soc/pci_devs.h>
#include <types.h>
/* SoC Overrides */
__weak void graphics_soc_init(struct device *dev)
@ -154,6 +155,16 @@ void graphics_gtt_rmw(unsigned long reg, uint32_t andmask, uint32_t ormask)
graphics_gtt_write(reg, val);
}
/*
* fsp_soc_get_igd_bar() is declared in <fsp/util.h>,
* but that draws incompatible UDK headers in.
*/
uintptr_t fsp_soc_get_igd_bar(void);
uintptr_t fsp_soc_get_igd_bar(void)
{
return graphics_get_memory_base();
}
static const struct device_operations graphics_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,

View File

@ -35,7 +35,6 @@ ramstage-y += espi.c
ramstage-y += finalize.c
ramstage-y += fsp_params.c
ramstage-y += gpio.c
ramstage-y += graphics.c
ramstage-y += lockdown.c
ramstage-y += p2sb.c
ramstage-y += pmc.c

View File

@ -1,10 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <fsp/util.h>
#include <intelblocks/graphics.h>
#include <types.h>
uintptr_t fsp_soc_get_igd_bar(void)
{
return graphics_get_memory_base();
}

View File

@ -36,7 +36,6 @@ ramstage-y += espi.c
ramstage-y += finalize.c
ramstage-y += fsp_params.c
ramstage-y += gpio.c
ramstage-y += graphics.c
ramstage-y += lockdown.c
ramstage-y += p2sb.c
ramstage-y += pmc.c

View File

@ -1,10 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <fsp/util.h>
#include <intelblocks/graphics.h>
#include <types.h>
uintptr_t fsp_soc_get_igd_bar(void)
{
return graphics_get_memory_base();
}

View File

@ -10,11 +10,6 @@
#include <soc/ramstage.h>
#include <types.h>
uintptr_t fsp_soc_get_igd_bar(void)
{
return graphics_get_memory_base();
}
void graphics_soc_init(struct device *dev)
{
struct soc_intel_skylake_config *conf = config_of(dev);

View File

@ -36,7 +36,6 @@ ramstage-y += espi.c
ramstage-y += finalize.c
ramstage-y += fsp_params.c
ramstage-y += gpio.c
ramstage-y += graphics.c
ramstage-y += lockdown.c
ramstage-y += p2sb.c
ramstage-y += pmc.c

View File

@ -1,16 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* This file is created based on Intel Tiger Lake Processor SA Datasheet
* Document number: 571131
* Chapter number: 4
*/
#include <fsp/util.h>
#include <intelblocks/graphics.h>
#include <types.h>
uintptr_t fsp_soc_get_igd_bar(void)
{
return graphics_get_memory_base();
}