update mp table and pirq table
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1337 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
parent
b020d53352
commit
bd4be244bb
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@ -45,7 +45,7 @@ default HAVE_HARD_RESET=1
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=7
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default IRQ_SLOT_COUNT=8
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##
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## Build code to export an x86 MP table
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@ -252,7 +252,7 @@ northbridge amd/amdk8 "mc0"
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pci 1:0.0 on
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pci 1:0.1 on
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pci 1:0.2 on
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pci 1:1.0 on
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# pci 1:1.0 off
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superio NSC/pc87360 link 1
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pnp 2e.0
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pnp 2e.1
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@ -1,31 +1,54 @@
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#include <arch/pirq_routing.h>
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#include <device/pci.h>
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#define IRQ_ROUTER_BUS 1
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#define IRQ_ROUTER_DEVFN PCI_DEVFN(5,0)
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#define IRQ_ROUTER_VENDOR 0x1022
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#define IRQ_ROUTER_DEVICE 0x7468
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#define IRQS_EXCLUSIVE 0x0c20
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#define IRQS_AVAILABLE 0xdeb8
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#define IRQ_SLOT(slot, bus, dev, fn, linka, linkb, linkc, linkd) \
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{ bus, (dev<<3)|fn, {{ linka, IRQS_AVAILABLE}, { linkb, IRQS_AVAILABLE}, \
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{linkc, IRQS_AVAILABLE}, {linkd, IRQS_AVAILABLE}}, slot, 0}
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/* Each IRQ_SLOT entry consists of:
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* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu
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*/
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*9, /* there can be total 9 devices on the bus */
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1, /* Where the interrupt router lies (bus) */
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(5<<3)|3, /* Where the interrupt router lies (dev) */
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0x0, /* IRQs devoted exclusively to PCI usage */
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0x1022, /* Vendor */
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0x7443, /* Device */
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0, /* Crap (miniport) */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0xb0, /* u8 checksum , mod 256 checksum must give zero */
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{ /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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/* PCI Slot 1 */
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{0x02, (0x01<<3)|0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x01, 0},
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/* PCI Slot 2 */
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{0x02, (0x02<<3)|0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}}, 0x02, 0},
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/* PCI Slot 3 */
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{0x01, (0x01<<3)|0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x03, 0},
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/* PCI Slot 4 */
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{0x01, (0x02<<3)|0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}}, 0x04, 0},
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/* PCI Slot 5 */
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{0x03, (0x05<<3)|0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x05, 0},
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/* PCI Slot 6 */
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{0x03, (0x04<<3)|0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}}, 0x06, 0},
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/* Let Linux know about bus 1 */
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{0x01, (0x05<<3)|3, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0},
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT
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* devices on the bus */
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IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */
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IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */
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IRQS_EXCLUSIVE, /* IRQs devoted exclusively to PCI usage */
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IRQ_ROUTER_VENDOR, /* Vendor */
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IRQ_ROUTER_DEVICE, /* Device */
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0x00, /* Crap (miniport) */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0x00, /* u8 checksum , mod 256 checksum must give
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* zero, will be corrected later
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*/
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{
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/* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */
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/* PCI SLOT 1-4 */
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IRQ_SLOT (1, 3,4,0, 1,2,3,4 ),
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IRQ_SLOT (2, 3,5,0, 2,3,4,1 ),
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IRQ_SLOT (3, 3,6,0, 3,4,1,2 ),
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IRQ_SLOT (4, 3,7,0, 4,1,2,3 ),
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/* Builtin Devices */
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IRQ_SLOT (0, 3,0,0, 4,4,4,4 ), /* USB */
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IRQ_SLOT (0, 1,5,1, 1,2,3,4 ), /* IDE */
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IRQ_SLOT (0, 1,2,0, 1,2,3,4 ), /* AGP Bridge */
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/* Let Linux know about bus 1 */
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IRQ_SLOT (0, 1,5,0, 0,0,0,0 ),
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}
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};
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@ -10,6 +10,10 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
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static const char oem[8] = "AMD ";
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static const char productid[12] = "SOLO7 ";
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struct mp_config_table *mc;
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unsigned char bus_num;
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unsigned char bus_isa;
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unsigned char bus_8151_1;
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unsigned char bus_8111_1;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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memset(mc, 0, sizeof(*mc));
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@ -30,79 +34,156 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
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smp_write_processors(mc, processor_map);
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smp_write_bus(mc, 0, "PCI ");
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smp_write_bus(mc, 1, "PCI ");
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smp_write_bus(mc, 2, "PCI ");
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smp_write_bus(mc, 3, "ISA ");
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{
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device_t dev;
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printk_info("creating mp table...\n");
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/* 8111 */
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dev = dev_find_slot(1, PCI_DEVFN(0x04,0));
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if (dev) {
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bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
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bus_isa++;
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printk_debug(" mptable: 8111 PCI bus %d\n", bus_8111_1);
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printk_debug(" mptable: 8111 ISA bus %d\n", bus_isa);
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}
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else {
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printk_debug("ERROR - could not find 8111 at PCI 1:04.0, using defaults\n");
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bus_8111_1 = 3;
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bus_isa = 4;
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}
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/* 8151-1 */
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dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
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if (dev) {
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bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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printk_debug(" mptable: 8151 PCI bus %d\n", bus_8151_1);
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}
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else {
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printk_debug("ERROR - could not find 8151 at PCI 1:01.0, using defaults\n");
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bus_8151_1 = 2;
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}
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}
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/* define bus and isa numbers */
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for(bus_num = 0; bus_num < bus_isa; bus_num++) {
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smp_write_bus(mc, bus_num, "PCI ");
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}
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smp_write_bus(mc, bus_isa, "ISA ");
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/* IOAPIC handling */
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smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
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/* ISA backward compatibility interrupts */
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smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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0x03, 0x00, 0x02, 0x00);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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0x03, 0x01, 0x02, 0x01);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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0x03, 0x00, 0x02, 0x02);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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0x03, 0x03, 0x02, 0x03);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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0x03, 0x04, 0x02, 0x04);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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0x03, 0x05, 0x02, 0x05);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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0x03, 0x06, 0x02, 0x06);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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0x03, 0x07, 0x02, 0x07);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
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0x03, 0x08, 0x02, 0x08);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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0x03, 0x09, 0x02, 0x09);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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0x03, 0x0a, 0x02, 0x0a);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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0x03, 0x0b, 0x02, 0x0b);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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0x03, 0x0c, 0x02, 0x0c);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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0x03, 0x0d, 0x02, 0x0d);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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0x03, 0x0e, 0x02, 0x0e);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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0x03, 0x0f, 0x02, 0x0f);
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bus_isa, 0x00, 0x02, 0x00);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x01, 0x02, 0x01);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x00, 0x02, 0x02);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x03, 0x02, 0x03);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x04, 0x02, 0x04);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x05, 0x02, 0x05);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x06, 0x02, 0x06);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x07, 0x02, 0x07);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x08, 0x02, 0x08);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x09, 0x02, 0x09);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0a, 0x02, 0x0a);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0b, 0x02, 0x0b);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0c, 0x02, 0x0c);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0d, 0x02, 0x0d);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0e, 0x02, 0x0e);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0f, 0x02, 0x0f);
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/* Standard local interrupt assignments */
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smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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0x03, 0x00, MP_APIC_ALL, 0x00);
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smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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0x00, 0x00, MP_APIC_ALL, 0x01);
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bus_isa, 0x00, MP_APIC_ALL, 0x00);
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smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x00, MP_APIC_ALL, 0x01);
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/* 8111 DevB.3 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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0x00, (5<<2)|3, 0x02, 0x13);
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/* AGP Slot */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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0x01, (0<<2)|0, 0x02, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8151_1, (0<<2)|0, 0x02, 0x10);
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/* PCI Slot 1 */
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#warning "FIXME get the irqs right, it's just hacked to work for now"
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8111_1, (4<<2)|0, 0x02, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8111_1, (4<<2)|1, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8111_1, (4<<2)|2, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8111_1, (4<<2)|3, 0x02, 0x10);
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/* PCI Slot 2 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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0x02, (5 <<2)|0, 0x02, 0x11);
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#warning "FIXME get the irqs right, it's just hacked to work for now"
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8111_1, (5<<2)|0, 0x02, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8111_1, (5<<2)|1, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8111_1, (5<<2)|2, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8111_1, (5<<2)|3, 0x02, 0x10);
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/* PCI Slot 3 */
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#warning "FIXME get the irqs right, it's just hacked to work for now"
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8111_1, (6<<2)|0, 0x02, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8111_1, (6<<2)|1, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8111_1, (6<<2)|2, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8111_1, (6<<2)|3, 0x02, 0x10);
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/* PCI Slot 4 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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0x02, (7<<2)|0, 0x02, 0x13);
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#warning "FIXME get the irqs right, it's just hacked to work for now"
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8111_1, (7<<2)|0, 0x02, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8111_1, (7<<2)|1, 0x02, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8111_1, (7<<2)|2, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8111_1, (7<<2)|3, 0x02, 0x13);
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/* AMR Slot */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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0x02, (1<<2)|0, 0x02, 0x10);
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/* Local devices */
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/* USB */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
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bus_8111_1, (0<<2)|3, 0x02, 0x13);
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/* Sound */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
1, (5<<2)|1, 0x02, 0x11);
|
||||
|
||||
|
||||
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
|
||||
|
||||
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
|
||||
printk_debug("Wrote the mp table end at: %p - %p\n",
|
||||
mc, smp_next_mpe_entry(mc));
|
||||
|
|
|
|||
Loading…
Reference in New Issue