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update mp table and pirq table 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1337 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2004-01-21 16:05:40 +00:00
parent b020d53352
commit bd4be244bb
3 changed files with 183 additions and 79 deletions
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4
src/mainboard/amd/solo/Config.lb
View File

@ -45,7 +45,7 @@ default HAVE_HARD_RESET=1
## Build code to export a programmable irq routing table ## Build code to export a programmable irq routing table
## ##
default HAVE_PIRQ_TABLE=1 default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=7 default IRQ_SLOT_COUNT=8
## ##
## Build code to export an x86 MP table ## Build code to export an x86 MP table
@ -252,7 +252,7 @@ northbridge amd/amdk8 "mc0"
pci 1:0.0 on pci 1:0.0 on
pci 1:0.1 on pci 1:0.1 on
pci 1:0.2 on pci 1:0.2 on
pci 1:1.0 on # pci 1:1.0 off
superio NSC/pc87360 link 1 superio NSC/pc87360 link 1
pnp 2e.0 pnp 2e.0
pnp 2e.1 pnp 2e.1

75
src/mainboard/amd/solo/irq_tables.c
View File

@ -1,31 +1,54 @@
#include <arch/pirq_routing.h> #include <arch/pirq_routing.h>
#include <device/pci.h>
#define IRQ_ROUTER_BUS 1
#define IRQ_ROUTER_DEVFN PCI_DEVFN(5,0)
#define IRQ_ROUTER_VENDOR 0x1022
#define IRQ_ROUTER_DEVICE 0x7468
#define IRQS_EXCLUSIVE 0x0c20
#define IRQS_AVAILABLE 0xdeb8
#define IRQ_SLOT(slot, bus, dev, fn, linka, linkb, linkc, linkd) \
{ bus, (dev<<3)|fn, {{ linka, IRQS_AVAILABLE}, { linkb, IRQS_AVAILABLE}, \
{linkc, IRQS_AVAILABLE}, {linkd, IRQS_AVAILABLE}}, slot, 0}
/* Each IRQ_SLOT entry consists of:
* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu
*/
const struct irq_routing_table intel_irq_routing_table = { const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */ PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */ PIRQ_VERSION, /* u16 version */
32+16*9, /* there can be total 9 devices on the bus */ 32+16*IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT
1, /* Where the interrupt router lies (bus) */ * devices on the bus */
(5<<3)|3, /* Where the interrupt router lies (dev) */ IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */
0x0, /* IRQs devoted exclusively to PCI usage */ IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */
0x1022, /* Vendor */ IRQS_EXCLUSIVE, /* IRQs devoted exclusively to PCI usage */
0x7443, /* Device */ IRQ_ROUTER_VENDOR, /* Vendor */
0, /* Crap (miniport) */ IRQ_ROUTER_DEVICE, /* Device */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0x00, /* Crap (miniport) */
0xb0, /* u8 checksum , mod 256 checksum must give zero */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
{ /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ 0x00, /* u8 checksum , mod 256 checksum must give
/* PCI Slot 1 */ * zero, will be corrected later
{0x02, (0x01<<3)|0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x01, 0}, */
/* PCI Slot 2 */ {
{0x02, (0x02<<3)|0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}}, 0x02, 0},
/* PCI Slot 3 */ /* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */
{0x01, (0x01<<3)|0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x03, 0},
/* PCI Slot 4 */ /* PCI SLOT 1-4 */
{0x01, (0x02<<3)|0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}}, 0x04, 0}, IRQ_SLOT (1, 3,4,0, 1,2,3,4 ),
/* PCI Slot 5 */ IRQ_SLOT (2, 3,5,0, 2,3,4,1 ),
{0x03, (0x05<<3)|0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x05, 0}, IRQ_SLOT (3, 3,6,0, 3,4,1,2 ),
/* PCI Slot 6 */ IRQ_SLOT (4, 3,7,0, 4,1,2,3 ),
{0x03, (0x04<<3)|0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}}, 0x06, 0},
/* Let Linux know about bus 1 */ /* Builtin Devices */
{0x01, (0x05<<3)|3, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x00, 0}, IRQ_SLOT (0, 3,0,0, 4,4,4,4 ), /* USB */
IRQ_SLOT (0, 1,5,1, 1,2,3,4 ), /* IDE */
IRQ_SLOT (0, 1,2,0, 1,2,3,4 ), /* AGP Bridge */
/* Let Linux know about bus 1 */
IRQ_SLOT (0, 1,5,0, 0,0,0,0 ),
} }
}; };

183
src/mainboard/amd/solo/mptable.c
View File

@ -10,6 +10,10 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
static const char oem[8] = "AMD "; static const char oem[8] = "AMD ";
static const char productid[12] = "SOLO7 "; static const char productid[12] = "SOLO7 ";
struct mp_config_table *mc; struct mp_config_table *mc;
unsigned char bus_num;
unsigned char bus_isa;
unsigned char bus_8151_1;
unsigned char bus_8111_1;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc)); memset(mc, 0, sizeof(*mc));
@ -30,79 +34,156 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
smp_write_processors(mc, processor_map); smp_write_processors(mc, processor_map);
smp_write_bus(mc, 0, "PCI "); {
smp_write_bus(mc, 1, "PCI "); device_t dev;
smp_write_bus(mc, 2, "PCI ");
smp_write_bus(mc, 3, "ISA "); printk_info("creating mp table...\n");
/* 8111 */
dev = dev_find_slot(1, PCI_DEVFN(0x04,0));
if (dev) {
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
printk_debug(" mptable: 8111 PCI bus %d\n", bus_8111_1);
printk_debug(" mptable: 8111 ISA bus %d\n", bus_isa);
}
else {
printk_debug("ERROR - could not find 8111 at PCI 1:04.0, using defaults\n");
bus_8111_1 = 3;
bus_isa = 4;
}
/* 8151-1 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
if (dev) {
bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
printk_debug(" mptable: 8151 PCI bus %d\n", bus_8151_1);
}
else {
printk_debug("ERROR - could not find 8151 at PCI 1:01.0, using defaults\n");
bus_8151_1 = 2;
}
}
/* define bus and isa numbers */
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
smp_write_bus(mc, bus_num, "PCI ");
}
smp_write_bus(mc, bus_isa, "ISA ");
/* IOAPIC handling */
smp_write_ioapic(mc, 2, 0x11, 0xfec00000); smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
/* ISA backward compatibility interrupts */ /* ISA backward compatibility interrupts */
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
0x03, 0x00, 0x02, 0x00); bus_isa, 0x00, 0x02, 0x00);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
0x03, 0x01, 0x02, 0x01); bus_isa, 0x01, 0x02, 0x01);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
0x03, 0x00, 0x02, 0x02); bus_isa, 0x00, 0x02, 0x02);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
0x03, 0x03, 0x02, 0x03); bus_isa, 0x03, 0x02, 0x03);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
0x03, 0x04, 0x02, 0x04); bus_isa, 0x04, 0x02, 0x04);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
0x03, 0x05, 0x02, 0x05); bus_isa, 0x05, 0x02, 0x05);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
0x03, 0x06, 0x02, 0x06); bus_isa, 0x06, 0x02, 0x06);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
0x03, 0x07, 0x02, 0x07); bus_isa, 0x07, 0x02, 0x07);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
0x03, 0x08, 0x02, 0x08); bus_isa, 0x08, 0x02, 0x08);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
0x03, 0x09, 0x02, 0x09); bus_isa, 0x09, 0x02, 0x09);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
0x03, 0x0a, 0x02, 0x0a); bus_isa, 0x0a, 0x02, 0x0a);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
0x03, 0x0b, 0x02, 0x0b); bus_isa, 0x0b, 0x02, 0x0b);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
0x03, 0x0c, 0x02, 0x0c); bus_isa, 0x0c, 0x02, 0x0c);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
0x03, 0x0d, 0x02, 0x0d); bus_isa, 0x0d, 0x02, 0x0d);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
0x03, 0x0e, 0x02, 0x0e); bus_isa, 0x0e, 0x02, 0x0e);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
0x03, 0x0f, 0x02, 0x0f); bus_isa, 0x0f, 0x02, 0x0f);
/* Standard local interrupt assignments */ /* Standard local interrupt assignments */
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
0x03, 0x00, MP_APIC_ALL, 0x00); bus_isa, 0x00, MP_APIC_ALL, 0x00);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
0x00, 0x00, MP_APIC_ALL, 0x01); bus_isa, 0x00, MP_APIC_ALL, 0x01);
/* 8111 DevB.3 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
0x00, (5<<2)|3, 0x02, 0x13);
/* AGP Slot */ /* AGP Slot */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
0x01, (0<<2)|0, 0x02, 0x10); bus_8151_1, (0<<2)|0, 0x02, 0x10);
/* PCI Slot 1 */ /* PCI Slot 1 */
#warning "FIXME get the irqs right, it's just hacked to work for now"
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (4<<2)|0, 0x02, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (4<<2)|1, 0x02, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (4<<2)|2, 0x02, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (4<<2)|3, 0x02, 0x10);
/* PCI Slot 2 */ /* PCI Slot 2 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, #warning "FIXME get the irqs right, it's just hacked to work for now"
0x02, (5 <<2)|0, 0x02, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (5<<2)|0, 0x02, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (5<<2)|1, 0x02, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (5<<2)|2, 0x02, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (5<<2)|3, 0x02, 0x10);
/* PCI Slot 3 */ /* PCI Slot 3 */
#warning "FIXME get the irqs right, it's just hacked to work for now"
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (6<<2)|0, 0x02, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (6<<2)|1, 0x02, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (6<<2)|2, 0x02, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (6<<2)|3, 0x02, 0x10);
/* PCI Slot 4 */ /* PCI Slot 4 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, #warning "FIXME get the irqs right, it's just hacked to work for now"
0x02, (7<<2)|0, 0x02, 0x13); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (7<<2)|0, 0x02, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (7<<2)|1, 0x02, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (7<<2)|2, 0x02, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8111_1, (7<<2)|3, 0x02, 0x13);
/* AMR Slot */ /* Local devices */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
0x02, (1<<2)|0, 0x02, 0x10);
/* USB */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_8111_1, (0<<2)|3, 0x02, 0x13);
/* Sound */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
1, (5<<2)|1, 0x02, 0x11);
/* There is no extension information... */ /* There is no extension information... */
/* Compute the checksums */ /* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk_debug("Wrote the mp table end at: %p - %p\n", printk_debug("Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc)); mc, smp_next_mpe_entry(mc));