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mb/system76: rtd3: Remove SrcClk pin on CPU RP 

Setting srcclk_pin only works for PCH PCIe devices. Disable them on the
CPU RP and add a TODO.

Change-Id: I32db116feb33a8448eb8586fe9e882b8879489d4
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
This commit is contained in:
Tim Crawford 2021-09-23 07:48:19 -06:00 committed by Felix Held
parent 9c120ef1d0
commit bd9b044a96
3 changed files with 6 additions and 3 deletions
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3
src/mainboard/system76/darp7/devicetree.cb
View File

@ -117,7 +117,8 @@ chip soc/intel/tigerlake
chip soc/intel/common/block/pcie/rtd3 chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" # SSD1_PWR_EN register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" # SSD1_PWR_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D13)" # GPP_D13_SSD1_PLT_RST# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D13)" # GPP_D13_SSD1_PLT_RST#
register "srcclk_pin" = "0" # SSD1_CLKREQ# # TODO: Support disable/enable CPU RP clock
register "srcclk_pin" = "-1" # SSD1_CLKREQ#
device generic 0 on end device generic 0 on end
end end
end end

3
src/mainboard/system76/galp5/devicetree.cb
View File

@ -117,7 +117,8 @@ chip soc/intel/tigerlake
chip soc/intel/common/block/pcie/rtd3 chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_DN# register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_DN#
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3
register "srcclk_pin" = "0" # SSD1_CLKREQ# # TODO: Support disable/enable CPU RP clock
register "srcclk_pin" = "-1" # SSD1_CLKREQ#
device generic 0 on end device generic 0 on end
end end
end end

3
src/mainboard/system76/lemp10/devicetree.cb
View File

@ -118,7 +118,8 @@ chip soc/intel/tigerlake
chip soc/intel/common/block/pcie/rtd3 chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C13)" # SSD1_PWR_DN# register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C13)" # SSD1_PWR_DN#
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)" # GPP_C12_RTD3 (labeled incorrectly) register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)" # GPP_C12_RTD3 (labeled incorrectly)
register "srcclk_pin" = "3" # TODO: Support disable/enable CPU RP clock
register "srcclk_pin" = "-1" # SSD2_CLKREQ#
device generic 0 on end device generic 0 on end
end end
end end