cpu/intel/haswell/acpi.c: Use C-state enum definitions
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change. Change-Id: I0ca98cbe45e10d233607f68923f08752fdda9698 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46923 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -15,15 +15,15 @@
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#include <southbridge/intel/lynxpoint/pch.h>
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static int cstate_set_lp[3] = {
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2,
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3,
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9,
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C_STATE_C1E,
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C_STATE_C3,
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C_STATE_C7S_LONG_LAT,
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};
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static int cstate_set_trad[3] = {
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1,
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3,
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5,
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C_STATE_C1,
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C_STATE_C3,
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C_STATE_C6_LONG_LAT,
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};
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static int get_cores_per_package(void)
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@ -125,6 +125,27 @@
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# error "CONFIG_IED_REGION_SIZE is not a power of 2"
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#endif
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/*
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* List of supported C-states for Haswell and Broadwell.
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* Only the ULT parts support C8, C9, and C10.
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*/
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enum {
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C_STATE_C0 = 0,
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C_STATE_C1 = 1,
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C_STATE_C1E = 2,
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C_STATE_C3 = 3,
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C_STATE_C6_SHORT_LAT = 4,
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C_STATE_C6_LONG_LAT = 5,
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C_STATE_C7_SHORT_LAT = 6,
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C_STATE_C7_LONG_LAT = 7,
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C_STATE_C7S_SHORT_LAT = 8,
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C_STATE_C7S_LONG_LAT = 9,
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C_STATE_C8 = 10,
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C_STATE_C9 = 11,
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C_STATE_C10 = 12,
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NUM_C_STATES,
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};
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/* Lock MSRs */
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void intel_cpu_haswell_finalize_smm(void);
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@ -20,27 +20,6 @@
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#include "haswell.h"
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#include "chip.h"
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/*
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* List of supported C-states in this processor. Only the ULT parts support C8,
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* C9, and C10.
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*/
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enum {
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C_STATE_C0, /* 0 */
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C_STATE_C1, /* 1 */
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C_STATE_C1E, /* 2 */
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C_STATE_C3, /* 3 */
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C_STATE_C6_SHORT_LAT, /* 4 */
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C_STATE_C6_LONG_LAT, /* 5 */
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C_STATE_C7_SHORT_LAT, /* 6 */
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C_STATE_C7_LONG_LAT, /* 7 */
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C_STATE_C7S_SHORT_LAT, /* 8 */
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C_STATE_C7S_LONG_LAT, /* 9 */
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C_STATE_C8, /* 10 */
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C_STATE_C9, /* 11 */
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C_STATE_C10, /* 12 */
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NUM_C_STATES
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};
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#define MWAIT_RES(state, sub_state) \
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{ \
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.addrl = (((state) << 4) | (sub_state)), \
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