cpu/intel/haswell/acpi.c: Use C-state enum definitions

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.

Change-Id: I0ca98cbe45e10d233607f68923f08752fdda9698
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46923
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-10-29 00:08:24 +01:00 committed by Patrick Georgi
parent ba5761a947
commit bda1c552e9
3 changed files with 27 additions and 27 deletions

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@ -15,15 +15,15 @@
#include <southbridge/intel/lynxpoint/pch.h>
static int cstate_set_lp[3] = {
2,
3,
9,
C_STATE_C1E,
C_STATE_C3,
C_STATE_C7S_LONG_LAT,
};
static int cstate_set_trad[3] = {
1,
3,
5,
C_STATE_C1,
C_STATE_C3,
C_STATE_C6_LONG_LAT,
};
static int get_cores_per_package(void)

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@ -125,6 +125,27 @@
# error "CONFIG_IED_REGION_SIZE is not a power of 2"
#endif
/*
* List of supported C-states for Haswell and Broadwell.
* Only the ULT parts support C8, C9, and C10.
*/
enum {
C_STATE_C0 = 0,
C_STATE_C1 = 1,
C_STATE_C1E = 2,
C_STATE_C3 = 3,
C_STATE_C6_SHORT_LAT = 4,
C_STATE_C6_LONG_LAT = 5,
C_STATE_C7_SHORT_LAT = 6,
C_STATE_C7_LONG_LAT = 7,
C_STATE_C7S_SHORT_LAT = 8,
C_STATE_C7S_LONG_LAT = 9,
C_STATE_C8 = 10,
C_STATE_C9 = 11,
C_STATE_C10 = 12,
NUM_C_STATES,
};
/* Lock MSRs */
void intel_cpu_haswell_finalize_smm(void);

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@ -20,27 +20,6 @@
#include "haswell.h"
#include "chip.h"
/*
* List of supported C-states in this processor. Only the ULT parts support C8,
* C9, and C10.
*/
enum {
C_STATE_C0, /* 0 */
C_STATE_C1, /* 1 */
C_STATE_C1E, /* 2 */
C_STATE_C3, /* 3 */
C_STATE_C6_SHORT_LAT, /* 4 */
C_STATE_C6_LONG_LAT, /* 5 */
C_STATE_C7_SHORT_LAT, /* 6 */
C_STATE_C7_LONG_LAT, /* 7 */
C_STATE_C7S_SHORT_LAT, /* 8 */
C_STATE_C7S_LONG_LAT, /* 9 */
C_STATE_C8, /* 10 */
C_STATE_C9, /* 11 */
C_STATE_C10, /* 12 */
NUM_C_STATES
};
#define MWAIT_RES(state, sub_state) \
{ \
.addrl = (((state) << 4) | (sub_state)), \