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nb/intel/gm45: Add C_ENVIRONMENT_BOOTBLOCK support 

The i82801ix_early_init is now called both in the bootblock and
romstage. The rationale behind setting this up twice is to ensure
bootblock-romstage compatibility in the future if for instance VBOOT
is used.

This moves the console init to the bootblock.

The romstage now runs uncached. Adding a prog_run hooks to set up an
MTRR to cache the romstage will be done in a followup patch.

The default size of 64KiB is not modified for the bootblock as trying
to fit both EHCI and SPI flash debugging needs a more space and 64KiB
is the next power of 2 size that fits it.

TESTED on Thinkpad X200.

Change-Id: I8f59736cb54377973215f35e35d2cbcd1d82c374
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Arthur Heymans 2019-10-12 14:35:25 +02:00 committed by Patrick Georgi
parent 942ad6a137
commit be9533aba9
17 changed files with 131 additions and 83 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/cpu/intel/socket_BGA956/Kconfig
View File

@ -14,4 +14,8 @@ config DCACHE_RAM_SIZE
hex
default 0x8000
config DCACHE_BSP_STACK_SIZE
hex
default 0x2000
endif

3
src/cpu/intel/socket_BGA956/Makefile.inc
View File

@ -8,7 +8,8 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep
cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
bootblock-y += ../car/core2/cache_as_ram.S
bootblock-y += ../car/bootblock.c
postcar-y += ../car/p4-netburst/exit_car.S
romstage-y += ../car/romstage.c

4
src/cpu/intel/socket_p/Kconfig
View File

@ -15,4 +15,8 @@ config DCACHE_RAM_SIZE
hex
default 0x8000
config DCACHE_BSP_STACK_SIZE
hex
default 0x2000
endif

3
src/cpu/intel/socket_p/Makefile.inc
View File

@ -9,7 +9,8 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep
cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
bootblock-y += ../car/core2/cache_as_ram.S
bootblock-y += ../car/bootblock.c
postcar-y += ../car/p4-netburst/exit_car.S
romstage-y += ../car/romstage.c

3
src/mainboard/lenovo/t400/Makefile.inc
View File

@ -13,7 +13,8 @@
## GNU General Public License for more details.
##
romstage-y += dock.c
bootblock-y += bootblock.c
bootblock-y += dock.c
subdirs-y += variants/$(VARIANT_DIR)/

37
src/mainboard/lenovo/t400/bootblock.c Normal file
View File

@ -0,0 +1,37 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <bootblock_common.h>
#include "dock.h"
static int dock_err;
void bootblock_mainboard_early_init(void)
{
/* Minimal setup to detect dock */
dock_err = pc87382_early();
if (dock_err == 0)
dock_connect();
}
void bootblock_mainboard_init(void)
{
/* Console is not yet initialized in bootblock_mainboard_early_init,
so we print the dock information here */
if (dock_err)
printk(BIOS_ERR, "DOCK: Failed to init pc87382\n");
else
dock_info();
}

18
src/mainboard/lenovo/t400/romstage.c
View File

@ -18,7 +18,6 @@
#include <southbridge/intel/common/gpio.h>
#include <northbridge/intel/gm45/gm45.h>
#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
#include "dock.h"
static void hybrid_graphics_init(sysinfo_t *sysinfo)
{
@ -30,16 +29,6 @@ static void hybrid_graphics_init(sysinfo_t *sysinfo)
sysinfo->enable_peg = peg;
}
static int dock_err;
void mb_setup_superio(void)
{
/* Minimal setup to detect dock */
dock_err = pc87382_early();
if (dock_err == 0)
dock_connect();
}
void get_mb_spd_addrmap(u8 *spd_addrmap)
{
spd_addrmap[0] = 0x50;
@ -48,13 +37,6 @@ void get_mb_spd_addrmap(u8 *spd_addrmap)
void mb_pre_raminit_setup(sysinfo_t *sysinfo)
{
/* Console is not yet initialized in mb_setup_superio, so we print
the dock information here */
if (dock_err)
printk(BIOS_ERR, "DOCK: Failed to init pc87382\n");
else
dock_info();
if (CONFIG(BOARD_LENOVO_R500)) {
int use_integrated = get_gpio(21);
printk(BIOS_DEBUG, "R500 variant found with an %s GPU\n",

2
src/mainboard/roda/rk9/Makefile.inc
View File

@ -13,6 +13,8 @@
## GNU General Public License for more details.
##
bootblock-y += bootblock.c
romstage-y = gpio.c
ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += ti_pci7xx1.c

63
src/mainboard/roda/rk9/bootblock.c Normal file
View File

@ -0,0 +1,63 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 secunet Security Networks AG
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <arch/io.h>
#include <device/pnp_ops.h>
#include <superio/smsc/lpc47n227/lpc47n227.h>
#define SERIAL_DEV PNP_DEV(0x2e, LPC47N227_SP1)
void bootblock_mainboard_early_init(void)
{
/* Original settings:
idx 30 31 32 33 34 35 36 37 38 39
val 60 00 00 40 00 ff 00 e0 00 80
def 00 00 00 00 00 00 00 00 00 80
Values:
GP1 GP2 GP3 GP4
fd 17 88 14
*/
const pnp_devfn_t sio = PNP_DEV(0x2e, 0);
/* Enter super-io's configuration state. */
pnp_enter_conf_state(sio);
/* Set lpc47n227's runtime register block's base address. */
pnp_write_config(sio, 0x30, 0x600 >> 4);
/* Set GP23 to alternate function. */
pnp_write_config(sio, 0x33, 0x40);
/* Set GP30 - GP37 to output mode: COM control */
pnp_write_config(sio, 0x35, 0xff);
/* Set GP45 - GP47 to output mode. */
pnp_write_config(sio, 0x37, 0xe0);
/* Set nIO_PME to open drain. */
pnp_write_config(sio, 0x39, 0x80);
/* Exit configuration state. */
pnp_exit_conf_state(sio);
/* Set GPIO output values: */
outb(0x88, 0x600 + 0xb + 3); /* GP30 - GP37 */
outb(0x10, 0x600 + 0xb + 4); /* GP40 - GP47 */
lpc47n227_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}

46
src/mainboard/roda/rk9/romstage.c
View File

@ -14,53 +14,7 @@
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <device/pnp_ops.h>
#include <northbridge/intel/gm45/gm45.h>
#include <superio/smsc/lpc47n227/lpc47n227.h>
#define SERIAL_DEV PNP_DEV(0x2e, LPC47N227_SP1)
void mb_setup_superio(void)
{
/* Original settings:
idx 30 31 32 33 34 35 36 37 38 39
val 60 00 00 40 00 ff 00 e0 00 80
def 00 00 00 00 00 00 00 00 00 80
Values:
GP1 GP2 GP3 GP4
fd 17 88 14
*/
const pnp_devfn_t sio = PNP_DEV(0x2e, 0);
/* Enter super-io's configuration state. */
pnp_enter_conf_state(sio);
/* Set lpc47n227's runtime register block's base address. */
pnp_write_config(sio, 0x30, 0x600 >> 4);
/* Set GP23 to alternate function. */
pnp_write_config(sio, 0x33, 0x40);
/* Set GP30 - GP37 to output mode: COM control */
pnp_write_config(sio, 0x35, 0xff);
/* Set GP45 - GP47 to output mode. */
pnp_write_config(sio, 0x37, 0xe0);
/* Set nIO_PME to open drain. */
pnp_write_config(sio, 0x39, 0x80);
/* Exit configuration state. */
pnp_exit_conf_state(sio);
/* Set GPIO output values: */
outb(0x88, 0x600 + 0xb + 3); /* GP30 - GP37 */
outb(0x10, 0x600 + 0xb + 4); /* GP40 - GP47 */
lpc47n227_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}
void get_mb_spd_addrmap(u8 *spd_addrmap)
{

5
src/northbridge/intel/gm45/Kconfig
View File

@ -26,15 +26,12 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select INTEL_GMA_ACPI
select INTEL_GMA_SSC_ALTERNATE_REF
select PARALLEL_MP
select C_ENVIRONMENT_BOOTBLOCK
config CBFS_SIZE
hex
default 0x100000
config BOOTBLOCK_NORTHBRIDGE_INIT
string
default "northbridge/intel/gm45/bootblock.c"
config VGA_BIOS_ID
string
default "8086,2a42"

2
src/northbridge/intel/gm45/Makefile.inc
View File

@ -15,6 +15,8 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_GM45),y)
bootblock-y += bootblock.c
romstage-y += early_init.c
romstage-y += early_reset.c
romstage-y += raminit.c

3
src/northbridge/intel/gm45/bootblock.c
View File

@ -11,13 +11,14 @@
* GNU General Public License for more details.
*/
#include <cpu/intel/car/bootblock.h>
#include <device/pci_ops.h>
/* Just re-define these instead of including gm45.h. It blows up romcc. */
#define D0F0_PCIEXBAR_LO 0x60
#define D0F0_PCIEXBAR_HI 0x64
static void bootblock_northbridge_init(void)
void bootblock_early_northbridge_init(void)
{
uint32_t reg;

6
src/northbridge/intel/gm45/romstage.c
View File

@ -62,12 +62,6 @@ void mainboard_romstage_entry(void)
i82801ix_early_init();
setup_pch_gpios(&mainboard_gpio_map);
i82801ix_lpc_decode();
mb_setup_superio();
console_init();
reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3);
pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16);
if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) {

4
src/southbridge/intel/i82801ix/Kconfig
View File

@ -47,8 +47,4 @@ config HPET_MIN_TICKS
hex
default 0x80
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/intel/i82801ix/bootblock.c"
endif

3
src/southbridge/intel/i82801ix/Makefile.inc
View File

@ -35,6 +35,9 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S
endif
smm-y += smihandler.c
bootblock-y += bootblock.c
bootblock-y += early_init.c
romstage-y += early_init.c
romstage-y += early_smbus.c
romstage-y += dmi_setup.c

8
src/southbridge/intel/i82801ix/bootblock.c
View File

@ -14,6 +14,9 @@
*/
#include <device/pci_ops.h>
#include <cpu/intel/car/bootblock.h>
#include "i82801ix.h"
static void enable_spi_prefetch(void)
{
@ -28,7 +31,10 @@ static void enable_spi_prefetch(void)
pci_write_config8(dev, 0xdc, reg8);
}
static void bootblock_southbridge_init(void)
void bootblock_early_southbridge_init(void)
{
enable_spi_prefetch();
i82801ix_early_init();
i82801ix_lpc_decode();
}