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mb/google/poppy: Disable SPI TPM 

Mainboard poppy is no longer using SPI TPM. This change disables GSPI0 in
device tree and udpates gpio configuration accordingly.

Change-Id: I713e41c45e323bf13aa79412ec679c90121a52b2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh 2017-12-04 12:16:22 -08:00 committed by Furquan Shaikh
parent df6b51baee
commit bea9b473d1
2 changed files with 2 additions and 47 deletions
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18
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
View File

@ -235,13 +235,6 @@ chip soc/intel/skylake
}"
# Use GSPI0 for cr50 TPM. Early init is required to set up a BAR for TPM
# communication before memory is up.
register "gspi[0]" = "{
.speed_mhz = 1,
.early_init = 1,
}"
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
@ -250,7 +243,7 @@ chip soc/intel/skylake
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
[PchSerialIoIndexSpi0] = PchSerialIoPci,
[PchSerialIoIndexSpi0] = PchSerialIoDisabled,
[PchSerialIoIndexSpi1] = PchSerialIoDisabled,
[PchSerialIoIndexUart0] = PchSerialIoPci,
[PchSerialIoIndexUart1] = PchSerialIoDisabled,
@ -374,14 +367,7 @@ chip soc/intel/skylake
device pci 1d.3 off end # PCI Express Port 12
device pci 1e.0 on end # UART #0
device pci 1e.1 off end # UART #1
device pci 1e.2 on
chip drivers/spi/acpi
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "compat_string" = ""google,cr50""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)"
device spi 0 on end
end
end # GSPI #0
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1
device pci 1e.4 on end # eMMC
device pci 1e.5 off end # SDIO

31
src/mainboard/google/poppy/variants/baseboard/gpio.c
View File

@ -92,16 +92,6 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
/* B14 : SPKR ==> NC */
PAD_CFG_NC(GPP_B14),
#if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM)
/* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
/* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */
PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
/* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
/* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
#else
/* B15 : GSPI0_CS# ==> NC */
PAD_CFG_NC(GPP_B15),
/* B16 : GSPI0_CLK ==> NC */
@ -110,7 +100,6 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NC(GPP_B17),
/* B18 : GSPI0_MOSI ==> NC */
PAD_CFG_NC(GPP_B18),
#endif
/* B19 : GSPI1_CS# ==> NC */
PAD_CFG_NC(GPP_B19),
/* B20 : GSPI1_CLK ==> NC */
@ -158,17 +147,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
/* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_3V3_SCL */
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
#if IS_ENABLED(CONFIG_POPPY_USE_I2C_TPM)
/* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
/* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
#else
/* C18 : I2C1_SDA ==> NC */
PAD_CFG_NC(GPP_C18),
/* C19 : I2C1_SCL ==> NC */
PAD_CFG_NC(GPP_C19),
#endif
/* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
/* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */
@ -371,23 +353,10 @@ static const struct pad_config gpio_table[] = {
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
#if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM)
/* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
/* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */
PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
/* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
/* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
#endif
#if IS_ENABLED(CONFIG_POPPY_USE_I2C_TPM)
/* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
/* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
#endif
/* Ensure UART pins are in native mode for H1. */
/* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */