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amdfam10 boards: Drop array bus_sb800 

Only bus_sb800[0] is evaluated.

Change-Id: I8ae0e6facbbe302b71692cf98a0292ee7d3bdca1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2019-01-03 11:39:01 +02:00
parent b30e2bfe34
commit bf2d227135
12 changed files with 12 additions and 84 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
src/mainboard/advansus/a785e-i/get_bus_conf.c
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@ -23,7 +23,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable /* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default. * and acpi_tables busnum is default.
*/ */
u8 bus_sb800[6];
u32 apicid_sb800; u32 apicid_sb800;
/* /*
@ -48,7 +47,6 @@ u32 hcdnx[] = {
void get_bus_conf(void) void get_bus_conf(void)
{ {
u32 apicid_base; u32 apicid_base;
struct device *dev;
int i; int i;
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
@ -61,22 +59,8 @@ void get_bus_conf(void)
sysconf.sbdn = (sysconf.hcdn[0] & 0xff); sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
memset(bus_sb800, 0, sizeof(bus_sb800));
bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* sb800 */
dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(0x14, 4));
if (dev) {
bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
for (i = 0; i < 4; i++) {
dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(0x15, i));
if (dev) {
bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
}
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) if (IS_ENABLED(CONFIG_LOGICAL_CPUS))

5
src/mainboard/advansus/a785e-i/irq_tables.c
View File

@ -39,7 +39,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
pirq_info->rfu = rfu; pirq_info->rfu = rfu;
} }
extern u8 bus_sb800[6];
unsigned long write_pirq_routing_table(unsigned long addr) unsigned long write_pirq_routing_table(unsigned long addr)
{ {
@ -64,7 +63,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->signature = PIRQ_SIGNATURE; pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION; pirq->version = PIRQ_VERSION;
pirq->rtr_bus = bus_sb800[0]; pirq->rtr_bus = pirq_router_bus;
pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
pirq->exclusive_irqs = 0; pirq->exclusive_irqs = 0;
@ -80,7 +79,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
slot_num = 0; slot_num = 0;
/* pci bridge */ /* pci bridge */
write_pirq_info(pirq_info, bus_sb800[0], PCI_DEVFN(0x14, 4), write_pirq_info(pirq_info, pirq_router_bus, PCI_DEVFN(0x14, 4),
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
0); 0);
pirq_info++; pirq_info++;

1
src/mainboard/advansus/a785e-i/mptable.c
View File

@ -20,7 +20,6 @@
#include <stdint.h> #include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h> #include <cpu/amd/amdfam10_sysconf.h>
extern u8 bus_sb800[6];
extern u32 apicid_sb800; extern u32 apicid_sb800;
u8 intr_data[] = { u8 intr_data[] = {

18
src/mainboard/amd/bimini_fam10/get_bus_conf.c
View File

@ -23,7 +23,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable /* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default. * and acpi_tables busnum is default.
*/ */
u8 bus_sb800[6];
u32 apicid_sb800; u32 apicid_sb800;
/* /*
@ -48,7 +47,6 @@ u32 hcdnx[] = {
void get_bus_conf(void) void get_bus_conf(void)
{ {
u32 apicid_base; u32 apicid_base;
struct device *dev;
int i; int i;
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
@ -61,22 +59,8 @@ void get_bus_conf(void)
sysconf.sbdn = (sysconf.hcdn[0] & 0xff); sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
memset(bus_sb800, 0, sizeof(bus_sb800));
bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* sb800 */
dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(0x14, 4));
if (dev) {
bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
for (i = 0; i < 4; i++) {
dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(0x15, i));
if (dev) {
bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
}
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) if (IS_ENABLED(CONFIG_LOGICAL_CPUS))

5
src/mainboard/amd/bimini_fam10/irq_tables.c
View File

@ -39,7 +39,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
pirq_info->rfu = rfu; pirq_info->rfu = rfu;
} }
extern u8 bus_sb800[6];
unsigned long write_pirq_routing_table(unsigned long addr) unsigned long write_pirq_routing_table(unsigned long addr)
{ {
@ -64,7 +63,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->signature = PIRQ_SIGNATURE; pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION; pirq->version = PIRQ_VERSION;
pirq->rtr_bus = bus_sb800[0]; pirq->rtr_bus = pirq_router_bus;
pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
pirq->exclusive_irqs = 0; pirq->exclusive_irqs = 0;
@ -80,7 +79,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
slot_num = 0; slot_num = 0;
/* pci bridge */ /* pci bridge */
write_pirq_info(pirq_info, bus_sb800[0], PCI_DEVFN(0x14, 4), write_pirq_info(pirq_info, pirq_router_bus, PCI_DEVFN(0x14, 4),
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
0); 0);
pirq_info++; pirq_info++;

1
src/mainboard/amd/bimini_fam10/mptable.c
View File

@ -21,7 +21,6 @@
#include <southbridge/amd/sb800/sb800.h> #include <southbridge/amd/sb800/sb800.h>
#include <cpu/amd/amdfam10_sysconf.h> #include <cpu/amd/amdfam10_sysconf.h>
extern u8 bus_sb800[6];
extern u32 apicid_sb800; extern u32 apicid_sb800;
u8 intr_data[] = { u8 intr_data[] = {

18
src/mainboard/asus/m5a88-v/get_bus_conf.c
View File

@ -23,7 +23,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable /* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default. * and acpi_tables busnum is default.
*/ */
u8 bus_sb800[6];
u32 apicid_sb800; u32 apicid_sb800;
/* /*
@ -48,7 +47,6 @@ u32 hcdnx[] = {
void get_bus_conf(void) void get_bus_conf(void)
{ {
u32 apicid_base; u32 apicid_base;
struct device *dev;
int i; int i;
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
@ -61,22 +59,8 @@ void get_bus_conf(void)
sysconf.sbdn = (sysconf.hcdn[0] & 0xff); sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
memset(bus_sb800, 0, sizeof(bus_sb800));
bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* sb800 */
dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(0x14, 4));
if (dev) {
bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
for (i = 0; i < 4; i++) {
dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(0x15, i));
if (dev) {
bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
}
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) if (IS_ENABLED(CONFIG_LOGICAL_CPUS))

5
src/mainboard/asus/m5a88-v/irq_tables.c
View File

@ -39,7 +39,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
pirq_info->rfu = rfu; pirq_info->rfu = rfu;
} }
extern u8 bus_sb800[6];
unsigned long write_pirq_routing_table(unsigned long addr) unsigned long write_pirq_routing_table(unsigned long addr)
{ {
@ -64,7 +63,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->signature = PIRQ_SIGNATURE; pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION; pirq->version = PIRQ_VERSION;
pirq->rtr_bus = bus_sb800[0]; pirq->rtr_bus = pirq_router_bus;
pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
pirq->exclusive_irqs = 0; pirq->exclusive_irqs = 0;
@ -80,7 +79,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
slot_num = 0; slot_num = 0;
/* pci bridge */ /* pci bridge */
write_pirq_info(pirq_info, bus_sb800[0], PCI_DEVFN(0x14, 4), write_pirq_info(pirq_info, pirq_router_bus, PCI_DEVFN(0x14, 4),
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
0); 0);
pirq_info++; pirq_info++;

1
src/mainboard/asus/m5a88-v/mptable.c
View File

@ -20,7 +20,6 @@
#include <stdint.h> #include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h> #include <cpu/amd/amdfam10_sysconf.h>
extern u8 bus_sb800[6];
extern u32 apicid_sb800; extern u32 apicid_sb800;
u8 intr_data[] = { u8 intr_data[] = {

18
src/mainboard/avalue/eax-785e/get_bus_conf.c
View File

@ -23,7 +23,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable /* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default. * and acpi_tables busnum is default.
*/ */
u8 bus_sb800[6];
u32 apicid_sb800; u32 apicid_sb800;
/* /*
@ -48,7 +47,6 @@ u32 hcdnx[] = {
void get_bus_conf(void) void get_bus_conf(void)
{ {
u32 apicid_base; u32 apicid_base;
struct device *dev;
int i; int i;
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
@ -61,22 +59,8 @@ void get_bus_conf(void)
sysconf.sbdn = (sysconf.hcdn[0] & 0xff); sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
memset(bus_sb800, 0, sizeof(bus_sb800));
bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* sb800 */
dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(0x14, 4));
if (dev) {
bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
for (i = 0; i < 4; i++) {
dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(0x15, i));
if (dev) {
bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
}
/* I/O APICs: APIC ID Version State Address */ /* I/O APICs: APIC ID Version State Address */
if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) if (IS_ENABLED(CONFIG_LOGICAL_CPUS))

5
src/mainboard/avalue/eax-785e/irq_tables.c
View File

@ -39,7 +39,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
pirq_info->rfu = rfu; pirq_info->rfu = rfu;
} }
extern u8 bus_sb800[6];
unsigned long write_pirq_routing_table(unsigned long addr) unsigned long write_pirq_routing_table(unsigned long addr)
{ {
@ -64,7 +63,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->signature = PIRQ_SIGNATURE; pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION; pirq->version = PIRQ_VERSION;
pirq->rtr_bus = bus_sb800[0]; pirq->rtr_bus = pirq_router_bus;
pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
pirq->exclusive_irqs = 0; pirq->exclusive_irqs = 0;
@ -80,7 +79,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
slot_num = 0; slot_num = 0;
/* pci bridge */ /* pci bridge */
write_pirq_info(pirq_info, bus_sb800[0], PCI_DEVFN(0x14, 4), write_pirq_info(pirq_info, pirq_router_bus, PCI_DEVFN(0x14, 4),
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
0); 0);
pirq_info++; pirq_info++;

1
src/mainboard/avalue/eax-785e/mptable.c
View File

@ -20,7 +20,6 @@
#include <stdint.h> #include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h> #include <cpu/amd/amdfam10_sysconf.h>
extern u8 bus_sb800[6];
extern u32 apicid_sb800; extern u32 apicid_sb800;
u8 intr_data[] = { u8 intr_data[] = {