mb/google/zork: Modify Woomax variant

Update Woomax configuration including GPIO, memory SPD table, I2C devices
and USB type C.

BUG=b:158343602
BRANCH=None
TEST=emerge-zork coreboot

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I55ba995d9438551d45cb9e17f92b5089ccf4a5fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Kane Chen 2020-07-16 13:36:20 +08:00 committed by Aaron Durbin
parent 3580d816e6
commit bfd6521ce7
5 changed files with 112 additions and 2 deletions

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@ -0,0 +1,33 @@
# Hynix-H5AN8G6NCJR-XNC
23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00
00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A
20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 9C B4 00 00 00 00 E7 00 75 20
0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80 AD 01 00 00 00 00 00 00 48 4D 41 38 35 31 53
36 43 4A 52 36 4A 2D 58 4E 20 20 20 20 00 80 AD
FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 DD 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

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@ -1,3 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-or-later # SPDX-License-Identifier: GPL-2.0-or-later
subdirs-y += ../baseboard/spd subdirs-y += ./spd
ramstage-y += gpio.c

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@ -0,0 +1,31 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/variants.h>
#include <soc/gpio.h>
static const struct soc_amd_gpio woomax_gpio_set_stage_ram[] = {
/* GPIO_4 NC */
PAD_NC(GPIO_4),
/* GPIO_5 NC */
PAD_NC(GPIO_5),
/* GPIO_6 NC */
PAD_NC(GPIO_6),
/* GPIO_11 NC */
PAD_NC(GPIO_11),
/* GPIO_32 NC */
PAD_NC(GPIO_32),
/* GPIO_69 NC */
PAD_NC(GPIO_69),
/* RAM_ID_4 */
PAD_NC(GPIO_84),
/* GPIO_141 NC */
PAD_NC(GPIO_141),
/* GPIO_143 NC */
PAD_NC(GPIO_143),
};
const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
{
*size = ARRAY_SIZE(woomax_gpio_set_stage_ram);
return woomax_gpio_set_stage_ram;
}

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@ -41,8 +41,34 @@ chip soc/amd/picasso
# See AMD 55570-B1 Table 13: PCI Device ID Assignments. # See AMD 55570-B1 Table 13: PCI Device ID Assignments.
device domain 0 on device domain 0 on
subsystemid 0x1022 0x1510 inherit subsystemid 0x1022 0x1510 inherit
chip drivers/usb/acpi
device usb 2.2 off end
end
chip drivers/usb/acpi
device usb 3.2 off end
end
end # domain end # domain
device mmio 0xfedc4000 on end device mmio 0xfedc4000 on
chip drivers/i2c/generic
register "hid" = ""ELAN0000""
register "desc" = ""ELAN Touchpad""
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)"
register "wake" = "GEVENT_22"
register "probed" = "1"
device i2c 15 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""ELAN9008""
register "generic.desc" = ""ELAN Touchscreen""
register "generic.probed" = "1"
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)"
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)"
register "generic.reset_delay_ms" = "20"
register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 10 on end
end
end
end # chip soc/amd/picasso end # chip soc/amd/picasso

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@ -0,0 +1,18 @@
# SPDX-License-Identifier: GPL-2.0-or-later
APCB_SOURCES = micron-MT40A512M16TB-062E-J_x1 # 0b00000
APCB_SOURCES += hynix-H5AN8G6NCJR-XNC_x1 # 0b00001
APCB_SOURCES += micron-MT40A1G16KD-062E-E_x1 # 0b00010
APCB_SOURCES += samsung-K4AAG165WA-BCWE_x1 # 0b00011
APCB_SOURCES += empty # 0b00100
APCB_SOURCES += empty # 0b00101
APCB_SOURCES += empty # 0b00110
APCB_SOURCES += empty # 0b00111
APCB_SOURCES += micron-MT40A512M16TB-062E-J_x2 # 0b01000
APCB_SOURCES += hynix-H5AN8G6NCJR-XNC_x2 # 0b01001
APCB_SOURCES += micron-MT40A1G16KD-062E-E_x2 # 0b01010
APCB_SOURCES += samsung-K4AAG165WA-BCWE_x2 # 0b01011
APCB_SOURCES += empty # 0b01100
APCB_SOURCES += empty # 0b01101
APCB_SOURCES += empty # 0b01110
APCB_SOURCES += empty # 0b01111