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ACPI: Use common OperationRegion for PCI_MMCONF 

Change-Id: Iadb4c3c77ecda4df8e48415d246e769ede2ce86d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50648
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2021-02-14 06:58:39 +02:00
parent c92efa3363
commit c0733e1639
6 changed files with 14 additions and 18 deletions
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13
src/acpi/dsdt_top.asl
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@ -32,9 +32,14 @@ Method (_PIC, 1)
} }
#if CONFIG(MMCONF_SUPPORT) #if CONFIG(MMCONF_SUPPORT)
/* Base address of PCIe config space */ Scope(\_SB) {
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)
/* Length of PCIe config space, 1MB each bus */ /* Length of PCIe config space, 1MB each bus */
Name(PCLN, CONFIG_MMCONF_LENGTH) Name(PCLN, CONFIG_MMCONF_LENGTH)
/* PCIe Configuration Space */
OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */
}
#endif #endif

2
src/soc/amd/stoneyridge/acpi/pci_int.asl
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@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */
OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */
Field(PCFG, ByteAcc, NoLock, Preserve) { Field(PCFG, ByteAcc, NoLock, Preserve) {
/* Byte offsets are computed using the following technique: /* Byte offsets are computed using the following technique:
* ((bus number + 1) * ((device number * 8) * 4096)) + register offset * ((bus number + 1) * ((device number * 8) * 4096)) + register offset

3
src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
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@ -284,8 +284,7 @@ Field( SMIC, ByteAcc, NoLock, Preserve) {
PGA3, 8 , PGA3, 8 ,
} }
OperationRegion(FCFG, SystemMemory, PCBA, 0x01000000) Field(PCFG, DwordAcc, NoLock, Preserve)
Field(FCFG, DwordAcc, NoLock, Preserve)
{ {
/* XHCI */ /* XHCI */
Offset(0x00080010), /* Base address */ Offset(0x00080010), /* Base address */

2
src/southbridge/amd/agesa/hudson/acpi/pci_int.asl
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@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */
OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */
Field(PCFG, ByteAcc, NoLock, Preserve) { Field(PCFG, ByteAcc, NoLock, Preserve) {
/* Byte offsets are computed using the following technique: /* Byte offsets are computed using the following technique:
* ((bus number + 1) * ((device number * 8) * 4096)) + register offset * ((bus number + 1) * ((device number * 8) * 4096)) + register offset

2
src/southbridge/amd/cimx/sb800/acpi/pcie.asl
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@ -29,8 +29,6 @@ Scope(\) {
} }
Scope(\_SB) { Scope(\_SB) {
/* PCIe Configuration Space for 16 busses */
OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
Field(PCFG, ByteAcc, NoLock, Preserve) { Field(PCFG, ByteAcc, NoLock, Preserve) {
/* Byte offsets are computed using the following technique: /* Byte offsets are computed using the following technique:
* ((bus number + 1) * ((device number * 8) * 4096)) + register offset * ((bus number + 1) * ((device number * 8) * 4096)) + register offset

2
src/southbridge/amd/pi/hudson/acpi/pci_int.asl
View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */
OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */
Field(PCFG, ByteAcc, NoLock, Preserve) { Field(PCFG, ByteAcc, NoLock, Preserve) {
/* Byte offsets are computed using the following technique: /* Byte offsets are computed using the following technique:
* ((bus number + 1) * ((device number * 8) * 4096)) + register offset * ((bus number + 1) * ((device number * 8) * 4096)) + register offset