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soc/intel/alderlake: set default PL4 values for different SKUs 

Set default PL4 values for various Alder Lake CPU SKUs as per
bug#191906315 comment#10.

BUG=b:194745919
BRANCH=None
TEST=Build FW and test on brya0 board.

Change-Id: I53791badbec3c165d56f20ce0656dc15d63bab37
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56917
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sumeet Pawnikar 2021-08-11 21:33:53 +05:30 committed by Felix Held
parent 191a8d7d2e
commit c0c477741d
1 changed files with 4 additions and 0 deletions
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4
src/soc/intel/alderlake/chipset.cb
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@ -5,21 +5,25 @@ chip soc/intel/alderlake
register "power_limits_config[ADL_P_POWER_LIMITS_282_CORE]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 55,
.tdp_pl4 = 123,
}"
register "power_limits_config[ADL_P_POWER_LIMITS_482_CORE]" = "{
.tdp_pl1_override = 28,
.tdp_pl2_override = 64,
.tdp_pl4 = 140,
}"
register "power_limits_config[ADL_P_POWER_LIMITS_682_CORE]" = "{
.tdp_pl1_override = 45,
.tdp_pl2_override = 115,
.tdp_pl4 = 215,
}"
register "power_limits_config[ADL_M_POWER_LIMITS_282_CORE]" = "{
.tdp_pl1_override = 9,
.tdp_pl2_override = 30,
.tdp_pl4 = 68,
}"
device domain 0 on