soc/intel/skylake: Use common opregion implementation
Enable SOC_INTEL_COMMON_GFX_OPREGION for all FSP versions. Allows to get rid of opregion.c, as it's no longer needed. Change-Id: I39190488e12917a09dbf7ee3947a33940ebc290b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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@ -83,6 +83,7 @@ config CPU_SPECIFIC_OPTIONS
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select UDELAY_TSC
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select UDELAY_TSC
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select ACPI_NHLT
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select ACPI_NHLT
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select HAVE_FSP_GOP
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select HAVE_FSP_GOP
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select SOC_INTEL_COMMON_GFX_OPREGION
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config MAINBOARD_USES_FSP2_0
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config MAINBOARD_USES_FSP2_0
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bool
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bool
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@ -93,7 +94,6 @@ config USE_FSP2_0_DRIVER
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depends on MAINBOARD_USES_FSP2_0
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depends on MAINBOARD_USES_FSP2_0
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select PLATFORM_USES_FSP2_0
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select PLATFORM_USES_FSP2_0
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select ADD_VBT_DATA_FILE if RUN_FSP_GOP
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select ADD_VBT_DATA_FILE if RUN_FSP_GOP
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select SOC_INTEL_COMMON_GFX_OPREGION
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select POSTCAR_CONSOLE
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select POSTCAR_CONSOLE
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select POSTCAR_STAGE
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select POSTCAR_STAGE
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@ -56,7 +56,6 @@ ramstage-y += irq.c
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ramstage-y += lpc.c
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ramstage-y += lpc.c
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ramstage-y += me.c
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ramstage-y += me.c
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ramstage-y += memmap.c
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ramstage-y += memmap.c
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ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += opregion.c
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ramstage-y += pch.c
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ramstage-y += pch.c
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ramstage-y += pei_data.c
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ramstage-y += pei_data.c
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ramstage-y += pmc.c
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ramstage-y += pmc.c
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@ -24,7 +24,7 @@
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#include <device/pci.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ids.h>
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#include <drivers/intel/gma/i915_reg.h>
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#include <drivers/intel/gma/i915_reg.h>
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#include <fsp/util.h>
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#include <soc/intel/common/opregion.h>
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#include <soc/acpi.h>
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#include <soc/acpi.h>
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#include <soc/cpu.h>
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#include <soc/cpu.h>
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#include <soc/pm.h>
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#include <soc/pm.h>
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@ -19,7 +19,6 @@
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#include <chip.h>
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#include <chip.h>
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#include <device/device.h>
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#include <device/device.h>
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#include <fsp/gop.h>
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#include <fsp/ramstage.h>
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#include <fsp/ramstage.h>
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#include <fsp/soc_binding.h>
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#include <fsp/soc_binding.h>
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@ -31,7 +30,6 @@ void pch_enable_dev(device_t dev);
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void soc_init_pre_device(void *chip_info);
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void soc_init_pre_device(void *chip_info);
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void soc_fsp_load(void);
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void soc_fsp_load(void);
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const char *soc_acpi_name(struct device *dev);
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const char *soc_acpi_name(struct device *dev);
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int init_igd_opregion(igd_opregion_t *igd_opregion);
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extern struct pci_operations soc_pci_ops;
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extern struct pci_operations soc_pci_ops;
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/* Get igd framebuffer bar */
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/* Get igd framebuffer bar */
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@ -1,50 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <soc/ramstage.h>
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#include <fsp/gop.h>
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#include <stdlib.h>
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#include <string.h>
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enum cb_err init_igd_opregion(igd_opregion_t *opregion)
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{
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const optionrom_vbt_t *vbt;
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uint32_t vbt_len;
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memset(opregion, 0, sizeof(igd_opregion_t));
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/* Read VBT table from flash */
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vbt = fsp_get_vbt(&vbt_len);
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if (!vbt)
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die("vbt data not found");
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memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
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sizeof(IGD_OPREGION_SIGNATURE) - 1);
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memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild,
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sizeof(u32));
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memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size <
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sizeof(opregion->vbt.gvd1) ? vbt->hdr_vbt_size :
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sizeof(opregion->vbt.gvd1));
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/* Size, in KB, of the entire OpRegion structure (including header)*/
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opregion->header.size = sizeof(igd_opregion_t) / KiB;
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opregion->header.version = IGD_OPREGION_VERSION;
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/* We just assume we're mobile for now */
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opregion->header.mailboxes = MAILBOXES_MOBILE;
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return CB_SUCCESS;
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}
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