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lynxpoint: expose iobp functions 

The iobp functions are useful to may of the southbridge
devices as certain values need to be updated to properly
initialize the devices. Therefore expose read, write, and
updated iobp functions.

Change-Id: Id7fdd8d0d9f022f92d6285ecd8f85a52024ec2bb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59275
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4249
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Aaron Durbin 2013-06-19 13:12:48 -05:00 committed by Alexandru Gagniuc
parent 91bd0b8419
commit c17aac32f2
2 changed files with 21 additions and 6 deletions
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25
src/southbridge/intel/lynxpoint/pch.c
View File

@ -201,7 +201,7 @@ static inline int iobp_poll(void)
return 0;
}
static u32 pch_iobp_read(u32 address)
u32 pch_iobp_read(u32 address)
{
u16 status;
@ -239,10 +239,15 @@ static u32 pch_iobp_read(u32 address)
return RCBA32(IOBPD);
}
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
void pch_iobp_write(u32 address, u32 data)
{
u16 status;
u32 data = pch_iobp_read(address);
if (!iobp_poll())
return;
/* Set the address */
RCBA32(IOBPIRI) = address;
/* WRITE OPCODE */
status = RCBA16(IOBPS);
@ -250,9 +255,6 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
status |= IOBPS_WRITE;
RCBA16(IOBPS) = status;
/* Update the data */
data &= andvalue;
data |= orvalue;
RCBA32(IOBPD) = data;
/* Undocumented magic */
@ -276,6 +278,17 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
printk(BIOS_INFO, "IOBP: set 0x%08x to 0x%08x\n", address, data);
}
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
{
u32 data = pch_iobp_read(address);
/* Update the data */
data &= andvalue;
data |= orvalue;
pch_iobp_write(address, data);
}
/* Check if any port in set X to X+3 is enabled */
static int pch_pcie_check_set_enabled(device_t dev)
{

2
src/southbridge/intel/lynxpoint/pch.h
View File

@ -162,6 +162,8 @@ void disable_gpe(u32 mask);
#include <arch/acpi.h>
#include "chip.h"
void pch_enable(device_t dev);
u32 pch_iobp_read(u32 address);
void pch_iobp_write(u32 address, u32 data);
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
#if CONFIG_ELOG
void pch_log_state(void);