soc/intel/skylake: Move Enable power button SMI code from smi.c to pmc.c
Original commit hash aeb2d64c85
(soc/intel/skylake:
Enable power button SMI when jumping to payload)
Change-Id: Ia4fe2694006baf24ed475c85aaffa6a0d2a6031d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22868
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -15,6 +15,7 @@
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* GNU General Public License for more details.
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*/
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#include <bootstate.h>
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#include <chip.h>
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#include <console/console.h>
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#include <device/device.h>
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@ -204,4 +205,19 @@ void pmc_soc_restore_power_failure(void)
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pmc_get_mainboard_power_failure_state_choice());
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}
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static void pm1_enable_pwrbtn_smi(void *unused)
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{
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/*
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* Enable power button SMI only before jumping to payload. This ensures
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* that:
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* 1. Power button SMI is enabled only after coreboot is done.
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* 2. On resume path, power button SMI is not enabled and thus avoids
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* any shutdowns because of power button presses due to power button
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* press in resume path.
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*/
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pmc_update_pm1_enable(PWRBTN_EN);
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}
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BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
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#endif
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@ -90,18 +90,3 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
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"d" (APM_CNT)
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);
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}
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static void pm1_enable_pwrbtn_smi(void *unused)
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{
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/*
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* Enable power button SMI only before jumping to payload. This ensures
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* that:
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* 1. Power button SMI is enabled only after coreboot is done.
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* 2. On resume path, power button SMI is not enabled and thus avoids
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* any shutdowns because of power button presses due to power button
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* press in resume path.
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*/
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pmc_update_pm1_enable(PWRBTN_EN);
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}
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BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
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