soc/intel/skylake: Move Enable power button SMI code from smi.c to pmc.c

Original commit hash aeb2d64c85 (soc/intel/skylake:
Enable power button SMI when jumping to payload)

Change-Id: Ia4fe2694006baf24ed475c85aaffa6a0d2a6031d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22868
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2017-12-14 16:28:45 +05:30
parent 7f4ec96869
commit c1d99c9962
2 changed files with 16 additions and 15 deletions

View File

@ -15,6 +15,7 @@
* GNU General Public License for more details.
*/
#include <bootstate.h>
#include <chip.h>
#include <console/console.h>
#include <device/device.h>
@ -204,4 +205,19 @@ void pmc_soc_restore_power_failure(void)
pmc_get_mainboard_power_failure_state_choice());
}
static void pm1_enable_pwrbtn_smi(void *unused)
{
/*
* Enable power button SMI only before jumping to payload. This ensures
* that:
* 1. Power button SMI is enabled only after coreboot is done.
* 2. On resume path, power button SMI is not enabled and thus avoids
* any shutdowns because of power button presses due to power button
* press in resume path.
*/
pmc_update_pm1_enable(PWRBTN_EN);
}
BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
#endif

View File

@ -90,18 +90,3 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
"d" (APM_CNT)
);
}
static void pm1_enable_pwrbtn_smi(void *unused)
{
/*
* Enable power button SMI only before jumping to payload. This ensures
* that:
* 1. Power button SMI is enabled only after coreboot is done.
* 2. On resume path, power button SMI is not enabled and thus avoids
* any shutdowns because of power button presses due to power button
* press in resume path.
*/
pmc_update_pm1_enable(PWRBTN_EN);
}
BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);