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soc/amd/mendocino: rename pwr_on_vary_bl_to_blon to edp_panel_t8_ms 

Rename the UPD pwr_on_vary_bl_to_blon to edp_panel_t8_ms to
match the eDP sequence timing in milliseconds.

BUG=b:271704149
BRANCH=Skyrim
Test=Build/Boot to ChromeOS

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Iecdfe47cd9142d8a1ddeee0ec988d37b2a11028e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74787
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Chris Wang 2023-04-26 19:27:54 +08:00 committed by Martin L Roth
parent 31e5133b63
commit c2059fa72a
4 changed files with 7 additions and 8 deletions
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4
src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
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@ -112,8 +112,8 @@ chip soc/amd/mendocino
register "dxio_tx_vboost_enable" = "1" register "dxio_tx_vboost_enable" = "1"
# The unit is set to one per 4ms # The unit is set to one per ms
register "pwr_on_vary_bl_to_blon" = "0x1c" register "edp_panel_t8_ms" = "112"
device ref gpp_bridge_1 on device ref gpp_bridge_1 on
# Required so the NVMe gets placed into D3 when entering S0i3. # Required so the NVMe gets placed into D3 when entering S0i3.

5
src/soc/amd/mendocino/chip.h
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@ -177,9 +177,8 @@ struct soc_amd_mendocino_config {
/* Force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1 */ /* Force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1 */
union usb3_force_gen1 usb3_port_force_gen1; union usb3_force_gen1 usb3_port_force_gen1;
/* Set for eDP power sequence adjustment timing from varybl to blon. The unit is set to /* Set for eDP power sequence adjustment timing T8 (from varybl to blon). */
one per 4ms*/ uint8_t edp_panel_t8_ms;
uint8_t pwr_on_vary_bl_to_blon;
}; };

2
src/soc/amd/mendocino/fsp_m_params.c
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@ -170,7 +170,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
} }
mcfg->dxio_tx_vboost_enable = config->dxio_tx_vboost_enable; mcfg->dxio_tx_vboost_enable = config->dxio_tx_vboost_enable;
mcfg->pwr_on_vary_bl_to_blon = config->pwr_on_vary_bl_to_blon; mcfg->edp_panel_t8_ms = config->edp_panel_t8_ms;
fsp_fill_pcie_ddi_descriptors(mcfg); fsp_fill_pcie_ddi_descriptors(mcfg);
fsp_assign_ioapic_upds(mcfg); fsp_assign_ioapic_upds(mcfg);

4
src/vendorcode/amd/fsp/mendocino/FspmUpd.h
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@ -101,8 +101,8 @@ typedef struct __packed {
/** Offset 0x04E1**/ uint32_t vrm_maximum_current_limit_mA; /** Offset 0x04E1**/ uint32_t vrm_maximum_current_limit_mA;
/** Offset 0x04E5**/ uint32_t vrm_soc_current_limit_mA; /** Offset 0x04E5**/ uint32_t vrm_soc_current_limit_mA;
/** Offset 0x04E9**/ uint8_t fch_usb_3_port_force_gen1; /** Offset 0x04E9**/ uint8_t fch_usb_3_port_force_gen1;
/** Offset 0x04E9**/ uint8_t pwr_on_vary_bl_to_blon; /** Offset 0x04EA**/ uint8_t edp_panel_t8_ms;
/** Offset 0x04EA**/ uint8_t UnusedUpdSpace2[277]; /** Offset 0x04EB**/ uint8_t UnusedUpdSpace2[277];
/** Offset 0x0600**/ uint16_t UpdTerminator; /** Offset 0x0600**/ uint16_t UpdTerminator;
} FSP_M_CONFIG; } FSP_M_CONFIG;