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soc/intel/alderlake: Implement PMC soft strap interface lock 

This patch performs locking of the PMC soft strap message interface.

BUG=b:211954778
TEST=Able to build and boot google/redrix to OS. Verified Bit 0 of PMC
MMIO register 0x104c is set as below.

> localhost ~ # iotools mmio_read32 0xfe00104c
0x00000001

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1ae972a203affa54c03de71f0f702356334cbf7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Subrata Banik 2022-04-20 13:10:47 +05:30 committed by Felix Held
parent f021952c40
commit c2570dc998
1 changed files with 3 additions and 1 deletions
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4
src/soc/intel/alderlake/lockdown.c
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@ -24,8 +24,10 @@ static void pmc_lockdown_cfg(int chipset_lockdown)
if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT)
setbits32(pmcbase + GEN_PMCON_B, SMI_LOCK); setbits32(pmcbase + GEN_PMCON_B, SMI_LOCK);
if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) {
setbits32(pmcbase + ST_PG_FDIS1, ST_FDIS_LOCK); setbits32(pmcbase + ST_PG_FDIS1, ST_FDIS_LOCK);
setbits32(pmcbase + SSML, SSML_SSL_EN);
}
} }
void soc_lockdown_config(int chipset_lockdown) void soc_lockdown_config(int chipset_lockdown)