x4x/i82801jx: Use common code for early SMBus
The early SMBus code for this chipset was not checking the vendor ID before. It is assumed that adding this check does not pose a problem. Change-Id: I0c36c8cd8aca8db860b1edafd29d4f2dbaa2c822 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42003 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -16,6 +16,7 @@ config SOUTHBRIDGE_INTEL_I82801JX
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select SOUTHBRIDGE_INTEL_COMMON_RESET
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select SOUTHBRIDGE_INTEL_COMMON_RTC
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select SOUTHBRIDGE_INTEL_COMMON_SMBUS
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select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
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select SOUTHBRIDGE_INTEL_COMMON_SMM
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select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
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select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
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@ -6,7 +6,6 @@ bootblock-y += bootblock.c
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bootblock-y += early_init.c
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romstage-y += early_init.c
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romstage-y += early_smbus.c
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ramstage-y += fadt.c
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ramstage-y += hdaudio.c
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@ -1,29 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <device/smbus_host.h>
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#include "i82801jx.h"
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uintptr_t smbus_base(void)
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{
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return CONFIG_FIXED_SMBUS_IO_BASE;
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}
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int smbus_enable_iobar(uintptr_t base)
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{
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/* Set the SMBus device statically. */
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pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
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/* Set SMBus I/O base. */
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pci_write_config32(dev, SMB_BASE,
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base | PCI_BASE_ADDRESS_SPACE_IO);
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/* Set SMBus enable. */
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pci_write_config8(dev, HOSTC, HST_EN);
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/* Set SMBus I/O space enable. */
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pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
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return 0;
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}
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