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Move RCBA defines to northbridge (instead of mainboard) 

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6074 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi 2010-11-15 19:44:42 +00:00 committed by Patrick Georgi
parent a69d978be8
commit c2bf26d247
2 changed files with 3 additions and 4 deletions
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5
src/mainboard/intel/eagleheights/romstage.c
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@ -39,6 +39,7 @@
#include "reset.c" #include "reset.c"
#include "superio/intel/i3100/i3100_early_serial.c" #include "superio/intel/i3100/i3100_early_serial.c"
#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
#include "northbridge/intel/i3100/i3100.h"
#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0) #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
@ -54,10 +55,6 @@
#define SATA_MODE_IDE 0x00 #define SATA_MODE_IDE 0x00
#define SATA_MODE_AHCI 0x01 #define SATA_MODE_AHCI 0x01
/* RCBA registers */
#define RCBA 0xF0
#define DEFAULT_RCBA 0xFEA00000
#define RCBA_RPC 0x0224 /* 32 bit */ #define RCBA_RPC 0x0224 /* 32 bit */
#define RCBA_TCTL 0x3000 /* 8 bit */ #define RCBA_TCTL 0x3000 /* 8 bit */

2
src/northbridge/intel/i3100/i3100.h
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@ -64,6 +64,8 @@
#define DRC_NOECC_MODE (0 << 20) #define DRC_NOECC_MODE (0 << 20)
#define DRC_72BIT_ECC (1 << 20) #define DRC_72BIT_ECC (1 << 20)
#define RCBA 0xF0
#define DEFAULT_RCBA 0xFEA00000
#ifdef __GNUC__ #ifdef __GNUC__
int bios_reset_detected(void); int bios_reset_detected(void);