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Lenovo ThinkPad X60: Clean up `romstage.c` 

1. Move comment for console init to correct place.
2. Start output with capital letter and add full stop at the end.
3. Add missing »)« at the end of description of GPIO 10.
4. Use tabulators instead of spaces.
5. Indent the code automatically using GNU indent [1] with the `-sc`
   switch adding stars in front of comment blocks as the good indent
   manual documents.

       $ indent -linux -sc src/mainboard/lenovo/x60/romstage.c

   Leave the numbers left aligned as it is more beneficial to be
   able to run indent without adapting the result afterward.

[1] http://www.coreboot.org/Development_Guidelines#Coding_Style

Change-Id: I2fa018ec28ff19d23d68754b565c13a7d7a57355
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3185
Tested-by: build bot (Jenkins)
Reviewed-by: Denis Carikli <GNUtoo@no-log.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Paul Menzel 2013-04-29 23:05:44 +02:00 committed by Ronald G. Minnich
parent ab98cfe110
commit c2f177737b
1 changed files with 36 additions and 32 deletions
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60
src/mainboard/lenovo/x60/romstage.c
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@ -43,27 +43,27 @@ void setup_ich7_gpios(void)
printk(BIOS_DEBUG, " GPIOS..."); printk(BIOS_DEBUG, " GPIOS...");
/* X60 GPIO: /* X60 GPIO:
1: HDD_PRESENCE# * 1: HDD_PRESENCE#
6: Unknown (Pulled high by R215 to VCC3B) * 6: Unknown (Pulled high by R215 to VCC3B)
7: BDC_PRESENCE# * 7: BDC_PRESENCE#
8: H8_WAKE# * 8: H8_WAKE#
9: RTC_BAT_IN# * 9: RTC_BAT_IN#
10: Unknown (Pulled high by R700 to VCC3M * 10: Unknown (Pulled high by R700 to VCC3M)
12: H8SCI# * 12: H8SCI#
13: SLICE_ON_3M# * 13: SLICE_ON_3M#
14: Unknown (Pulled high by R321 to VCC3) * 14: Unknown (Pulled high by R321 to VCC3)
15: Unknown (Pulled high by R258 to VCC3) * 15: Unknown (Pulled high by R258 to VCC3)
19: Unknown (Pulled low by R594) * 19: Unknown (Pulled low by R594)
21: Unknown (Pulled high by R145 to VCC3) * 21: Unknown (Pulled high by R145 to VCC3)
22: FWH_WP# * 22: FWH_WP#
25: MDC_KILL# * 25: MDC_KILL#
33: HDD_PRESENCE_2# * 33: HDD_PRESENCE_2#
35: CLKREQ_SATA# * 35: CLKREQ_SATA#
36: PLANARID0 * 36: PLANARID0
37: PLANARID1 * 37: PLANARID1
38: PLANARID2 * 38: PLANARID2
39: PLANARID3 * 39: PLANARID3
48: FWH_TBL# * 48: FWH_TBL#
*/ */
outl(0x1f40f7c2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ outl(0x1f40f7c2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
@ -107,7 +107,7 @@ static void early_superio_config(void)
pnp_write_config(dev, 0x29, 0x06); pnp_write_config(dev, 0x29, 0x06);
while(!(pnp_read_config(dev, 0x29) & 0x08) && timeout--) while (!(pnp_read_config(dev, 0x29) & 0x08) && timeout--)
udelay(1000); udelay(1000);
/* Enable COM1 */ /* Enable COM1 */
@ -236,18 +236,20 @@ void main(unsigned long bist)
if (dock_present()) { if (dock_present()) {
dock_connect(); dock_connect();
early_superio_config(); early_superio_config();
/* Set up the console */
} }
/* Set up the console */
console_init(); console_init();
/* Halt if there was a built in self test failure */ /* Halt if there was a built in self test failure */
report_bist_failure(bist); report_bist_failure(bist);
if (MCHBAR16(SSKPD) == 0xCAFE) { if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); printk(BIOS_DEBUG,
"Soft reset detected, rebooting properly.\n");
outb(0x6, 0xcf9); outb(0x6, 0xcf9);
while (1) asm("hlt"); while (1)
asm("hlt");
} }
/* Perform some early chipset initialization required /* Perform some early chipset initialization required
@ -302,7 +304,7 @@ void main(unsigned long bist)
{ {
/* This will not work if TSEG is in place! */ /* This will not work if TSEG is in place! */
u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), 0x5c);
printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
ram_check(0x00000000, 0x000a0000); ram_check(0x00000000, 0x000a0000);
@ -329,10 +331,12 @@ void main(unsigned long bist)
* day. * day.
*/ */
if (resume_backup_memory) if (resume_backup_memory)
memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE,
HIGH_MEMORY_SAVE);
/* Magic for S3 resume */ /* Magic for S3 resume */
pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC); pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD,
SKPAD_ACPI_S3_MAGIC);
} }
#endif #endif