GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

AGESA: Fix CR0_PE bit define 

AGESA code has wrong definition of CR0_PE bit (1 instead of 0).

PE [Protected Mode Enable] is 0 bit in CR0 register
(If PE=1, system is in protected mode, else system is in real mode)

Bit 1 is MP [Monitor co-processor]
(Controls interaction of WAIT/FWAIT instructions with TS flag in CR0)

System uses CR0_PE define, but I didn't expect any consequences because of this bug.

Change-Id: I54d9a8c0ee3af0a2e0267777036f227a9e05f3e1
Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/2591
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
Konstantin Aladyshev 2013-03-06 22:13:42 +04:00 committed by Marc Jones
parent 4c1e906e36
commit c2f2bd0a6d
5 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/vendorcode/amd/agesa/f10/gcccar.inc
View File

@ -100,7 +100,7 @@ CU_CFG3 = 0x0C001102B /* Combined Unit Configuration
COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */ COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */
CR0_PE = 1 # Protection Enable CR0_PE = 0 # Protection Enable
CR0_NW = 29 # Not Write-through CR0_NW = 29 # Not Write-through
CR0_CD = 30 # Cache Disable CR0_CD = 30 # Cache Disable
CR0_PG = 31 # Paging Enable CR0_PG = 31 # Paging Enable

2
src/vendorcode/amd/agesa/f12/gcccar.inc
View File

@ -100,7 +100,7 @@ CU_CFG3 = 0x0C001102B /* Combined Unit Configuration
COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */ COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */
CR0_PE = 1 # Protection Enable CR0_PE = 0 # Protection Enable
CR0_NW = 29 # Not Write-through CR0_NW = 29 # Not Write-through
CR0_CD = 30 # Cache Disable CR0_CD = 30 # Cache Disable
CR0_PG = 31 # Paging Enable CR0_PG = 31 # Paging Enable

2
src/vendorcode/amd/agesa/f14/cpcar.inc
View File

@ -97,7 +97,7 @@ CU_CFG3 EQU 0C001102Bh ; Combined Unit Configuration 3
COMBINE_CR0_CD EQU 49 ; Combine CR0.CD for both cores of a compute unit COMBINE_CR0_CD EQU 49 ; Combine CR0.CD for both cores of a compute unit
CR0_PE EQU 1 ; Protection Enable CR0_PE EQU 0 ; Protection Enable
CR0_NW EQU 29 ; Not Write-through CR0_NW EQU 29 ; Not Write-through
CR0_CD EQU 30 ; Cache Disable CR0_CD EQU 30 ; Cache Disable
CR0_PG EQU 31 ; Paging Enable CR0_PG EQU 31 ; Paging Enable

2
src/vendorcode/amd/agesa/f14/gcccar.inc
View File

@ -114,7 +114,7 @@ CU_CFG3 = 0x0C001102B /* Combined Unit Configuration
COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */ COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */
CR0_PE = 1 # Protection Enable CR0_PE = 0 # Protection Enable
CR0_NW = 29 # Not Write-through CR0_NW = 29 # Not Write-through
CR0_CD = 30 # Cache Disable CR0_CD = 30 # Cache Disable
CR0_PG = 31 # Paging Enable CR0_PG = 31 # Paging Enable

2
src/vendorcode/amd/agesa/f15/gcccar.inc
View File

@ -115,7 +115,7 @@ CU_CFG3 = 0x0C001102B /* Combined Unit Configuration
COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */ COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */
CR0_PE = 1 # Protection Enable CR0_PE = 0 # Protection Enable
CR0_NW = 29 # Not Write-through CR0_NW = 29 # Not Write-through
CR0_CD = 30 # Cache Disable CR0_CD = 30 # Cache Disable
CR0_PG = 31 # Paging Enable CR0_PG = 31 # Paging Enable