Update PCIe Root Port _PRT to handle re-mapped functions
The chipset enforces static-defined interrupt swizzling on PCIe root ports so if a port is remapped to a different function it needs to still report the proper interrupt map to the OS instead of assuming that function number is equivalent to root port number. This change also includes an update to the PCH function disable register which was incorrect for CPT/PPT and would cause unpredictable behavior if used. The kernel command line was changed to add 'nomsi' in order to force PCIe devices to use IO-APIC assigned interrupts and not MSI to ensure that the mapping is correct. LUMPY current: 00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5) 00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5) 16: 41518 0 0 0 IO-APIC-fasteoi i915, ahci, ath9k 19: 720 0 0 0 IO-APIC-fasteoi ehci_hcd:usb2, eth0 LUMPY with PCIe port coalesce enabled: 00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5) 00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5) 16: 38988 0 0 0 IO-APIC-fasteoi i915, ahci, ath9k 19: 347 0 0 0 IO-APIC-fasteoi ehci_hcd:usb2, eth0 Change-Id: Ia5f6bb8888b5c38a5dbc88bb25ecdf1fca41ee3e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/978 Tested-by: build bot (Jenkins)
This commit is contained in:
Duncan Laurie
Stefan Reinauer
parent
2c41c4027f
commit
c323036884
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@ -211,26 +211,32 @@ Scope(\)
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, 5,
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HPTE, 1, // Address Enable
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Offset(0x3418), // FD (Function Disable)
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, 2, // Reserved
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SATD, 1, // SATA disable
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, 1, // Reserved
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PCID, 1, // PCI bridge disable
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SA1D, 1, // SATA1 disable
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SMBD, 1, // SMBUS disable
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HDAD, 1, // Azalia disable
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, 2, // Reserved
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ILND, 1, // Internal LAN disable
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US1D, 1, // UHCI #1 disable
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US2D, 1, // UHCI #2 disable
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US3D, 1, // UHCI #3 disable
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US4D, 1, // UHCI #4 disable
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, 2, // Reserved
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, 8, // Reserved
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EH2D, 1, // EHCI #2 disable
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LPBD, 1, // LPC bridge disable
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EHCD, 1, // EHCI disable
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Offset(0x341a), // FD Root Ports
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EH1D, 1, // EHCI #1 disable
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RP1D, 1, // Root Port 1 disable
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RP2D, 1, // Root Port 2 disable
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RP3D, 1, // Root Port 3 disable
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RP4D, 1 // Root Port 4 disable
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RP4D, 1, // Root Port 4 disable
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RP5D, 1, // Root Port 5 disable
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RP6D, 1, // Root Port 6 disable
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RP7D, 1, // Root Port 7 disable
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RP8D, 1, // Root Port 8 disable
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TTRD, 1, // Thermal sensor registers disable
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SA2D, 1, // SATA2 disable
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Offset(0x3428), // FD2 (Function Disable 2)
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BDFD, 1, // Display BDF
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ME1D, 1, // ME Interface 1 disable
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ME2D, 1, // ME Interface 2 disable
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IDRD, 1, // IDE redirect disable
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KTCT, 1, // Keyboard Text redirect disable
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}
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}
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// High Definition Audio (Azalia) 0:1b.0
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@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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@ -19,216 +20,199 @@
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* MA 02110-1301 USA
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*/
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/* Intel Cougar Point PCH PCIe support */
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/* Intel 6/7 Series PCH PCIe support */
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// PCI Express Ports
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Device (RP01)
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{
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NAME(_ADR, 0x001c0000) // FIXME: Have a macro for PCI Devices -> ACPI notation?
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//#include "pcie_port.asl"
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Method(_PRT)
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{
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If (PICM) {
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Return (Package() {
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Method (IRQM, 1, Serialized) {
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/* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */
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Name (IQAA, Package() {
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Package() { 0x0000ffff, 0, 0, 16 },
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Package() { 0x0000ffff, 1, 0, 17 },
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Package() { 0x0000ffff, 2, 0, 18 },
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Package() { 0x0000ffff, 3, 0, 19 }
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})
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} Else {
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Return (Package() {
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Package() { 0x0000ffff, 3, 0, 19 } })
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Name (IQAP, Package() {
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Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }
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})
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Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } })
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/* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */
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Name (IQBA, Package() {
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Package() { 0x0000ffff, 0, 0, 17 },
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Package() { 0x0000ffff, 1, 0, 18 },
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Package() { 0x0000ffff, 2, 0, 19 },
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Package() { 0x0000ffff, 3, 0, 16 } })
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Name (IQBP, Package() {
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Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
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Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } })
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/* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */
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Name (IQCA, Package() {
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Package() { 0x0000ffff, 0, 0, 18 },
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Package() { 0x0000ffff, 1, 0, 19 },
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Package() { 0x0000ffff, 2, 0, 16 },
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Package() { 0x0000ffff, 3, 0, 17 } })
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Name (IQCP, Package() {
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Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
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Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 } })
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/* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */
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Name (IQDA, Package() {
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Package() { 0x0000ffff, 0, 0, 19 },
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Package() { 0x0000ffff, 1, 0, 16 },
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Package() { 0x0000ffff, 2, 0, 17 },
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Package() { 0x0000ffff, 3, 0, 18 } })
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Name (IQDP, Package() {
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Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
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Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 } })
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Switch (ToInteger (Arg0)) {
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/* PCIe Root Port 1 and 5 */
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Case (Package() { 1, 5 }) {
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If (PICM) {
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Return (IQAA)
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} Else {
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Return (IQAP)
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}
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}
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/* PCIe Root Port 2 and 6 */
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Case (Package() { 2, 6 }) {
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If (PICM) {
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Return (IQBA)
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} Else {
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Return (IQBP)
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}
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}
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/* PCIe Root Port 3 and 7 */
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Case (Package() { 3, 7 }) {
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If (PICM) {
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Return (IQCA)
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} Else {
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Return (IQCP)
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}
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}
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/* PCIe Root Port 4 and 8 */
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Case (Package() { 4, 8 }) {
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If (PICM) {
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Return (IQDA)
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} Else {
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Return (IQDP)
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}
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}
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Default {
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If (PICM) {
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Return (IQDA)
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} Else {
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Return (IQDP)
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}
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}
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}
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}
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Device (RP01)
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{
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Name (_ADR, 0x001c0000)
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#include "pcie_port.asl"
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Method (_PRT)
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{
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Return (IRQM (RPPN))
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}
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}
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Device (RP02)
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{
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NAME(_ADR, 0x001c0001) // FIXME: Have a macro for PCI Devices -> ACPI notation?
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//#include "pcie_port.asl"
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Name (_ADR, 0x001c0001)
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#include "pcie_port.asl"
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Method (_PRT)
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{
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If (PICM) {
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Return (Package() {
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Package() { 0x0000ffff, 0, 0, 17 },
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Package() { 0x0000ffff, 1, 0, 18 },
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Package() { 0x0000ffff, 2, 0, 19 },
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Package() { 0x0000ffff, 3, 0, 16 }
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})
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} Else {
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Return (Package() {
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Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
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Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }
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})
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}
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Return (IRQM (RPPN))
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}
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}
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Device (RP03)
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{
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NAME(_ADR, 0x001c0002) // FIXME: Have a macro for PCI Devices -> ACPI notation?
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//#include "pcie_port.asl"
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Name (_ADR, 0x001c0002)
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#include "pcie_port.asl"
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Method (_PRT)
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{
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If (PICM) {
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Return (Package() {
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Package() { 0x0000ffff, 0, 0, 18 },
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Package() { 0x0000ffff, 1, 0, 19 },
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Package() { 0x0000ffff, 2, 0, 16 },
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Package() { 0x0000ffff, 3, 0, 17 }
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})
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} Else {
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Return (Package() {
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Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
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Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 }
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})
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}
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Return (IRQM (RPPN))
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}
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}
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Device (RP04)
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{
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NAME(_ADR, 0x001c0003) // FIXME: Have a macro for PCI Devices -> ACPI notation?
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//#include "pcie_port.asl"
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Name (_ADR, 0x001c0003)
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#include "pcie_port.asl"
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Method (_PRT)
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{
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If (PICM) {
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Return (Package() {
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Package() { 0x0000ffff, 0, 0, 17 },
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Package() { 0x0000ffff, 1, 0, 18 },
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Package() { 0x0000ffff, 2, 0, 19 },
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Package() { 0x0000ffff, 3, 0, 16 }
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})
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} Else {
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Return (Package() {
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Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
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Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }
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})
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}
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Return (IRQM (RPPN))
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}
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}
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Device (RP05)
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{
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NAME(_ADR, 0x001c0004) // FIXME: Have a macro for PCI Devices -> ACPI notation?
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//#include "pcie_port.asl"
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Name (_ADR, 0x001c0004)
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#include "pcie_port.asl"
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Method (_PRT)
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{
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If (PICM) {
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Return (Package() {
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Package() { 0x0000ffff, 0, 0, 16 },
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Package() { 0x0000ffff, 1, 0, 17 },
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Package() { 0x0000ffff, 2, 0, 18 },
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Package() { 0x0000ffff, 3, 0, 19 }
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})
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} Else {
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Return (Package() {
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Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }
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})
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}
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Return (IRQM (RPPN))
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}
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}
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Device (RP06)
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{
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NAME(_ADR, 0x001c0005) // FIXME: Have a macro for PCI Devices -> ACPI notation?
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//#include "pcie_port.asl"
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Name (_ADR, 0x001c0005)
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#include "pcie_port.asl"
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Method (_PRT)
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{
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If (PICM) {
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Return (Package() {
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Package() { 0x0000ffff, 0, 0, 17 },
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Package() { 0x0000ffff, 1, 0, 18 },
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Package() { 0x0000ffff, 2, 0, 19 },
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Package() { 0x0000ffff, 3, 0, 16 }
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})
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} Else {
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Return (Package() {
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Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
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Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }
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})
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}
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Return (IRQM (RPPN))
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}
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}
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Device (RP07)
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{
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NAME(_ADR, 0x001c0006) // FIXME: Have a macro for PCI Devices -> ACPI notation?
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//#include "pcie_port.asl"
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Name (_ADR, 0x001c0006)
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#include "pcie_port.asl"
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Method (_PRT)
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{
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If (PICM) {
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Return (Package() {
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Package() { 0x0000ffff, 0, 0, 18 },
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Package() { 0x0000ffff, 1, 0, 19 },
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Package() { 0x0000ffff, 2, 0, 16 },
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Package() { 0x0000ffff, 3, 0, 17 }
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})
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} Else {
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Return (Package() {
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Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
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Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 }
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})
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}
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Return (IRQM (RPPN))
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}
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}
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Device (RP08)
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{
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NAME(_ADR, 0x001c0007) // FIXME: Have a macro for PCI Devices -> ACPI notation?
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//#include "pcie_port.asl"
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Name (_ADR, 0x001c0007)
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#include "pcie_port.asl"
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Method (_PRT)
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{
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If (PICM) {
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Return (Package() {
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Package() { 0x0000ffff, 0, 0, 19 },
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Package() { 0x0000ffff, 1, 0, 16 },
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Package() { 0x0000ffff, 2, 0, 17 },
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Package() { 0x0000ffff, 3, 0, 18 }
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})
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} Else {
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Return (Package() {
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Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
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Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }
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})
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}
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Return (IRQM (RPPN))
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}
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}
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|
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@ -0,0 +1,30 @@
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/*
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* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
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*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
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* MA 02110-1301 USA
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||||
*/
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/* Included in each PCIe Root Port device */
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OperationRegion (RPCS, PCI_Config, 0x00, 0xFF)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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Offset (0x4c), // Link Capabilities
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, 24,
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RPPN, 8, // Root Port Number
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}
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