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soc/amd/sabrina: update soft fuse bit 15 definition 

For SoC that don't support LPC any more the definition of the PSP soft
fuse chain bit 15 has changed. Earlier SoCs that still supported a
physical LPC bus used this bit to determine if the I/O port 0x80 POST
code are sent to LPC or eSPI. Newer SoCs like Sabrina don't have a
physical LPC bus any more and on those this bit selects if the PSP debug
output is sent to the SoC's MMIO UART or an UART on I/O port 0x3F8 that
the needs to be decoded to eSPI.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0bffb6efacc585a1d02a0455b32f7cf8662b3232
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held 2022-03-23 22:15:56 +01:00
parent 24d40fd698
commit c35790012f
2 changed files with 2 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/soc/amd/sabrina/Kconfig
View File

@ -399,8 +399,8 @@ config PSP_SOFTFUSE_BITS
Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG)
Bit 7: Disable PSP postcodes on Renoir and newer chips only
(Set by PSP_DISABLE_PORT80)
Bit 15: PSP post code destination: 0=LPC 1=eSPI
(Set by PSP_INITIALIZE_ESPI)
Bit 15: PSP debug output destination:
0=SoC MMIO UART, 1=IO port 0x3F8
Bit 29: Disable MP2 firmware loading (Set by PSP_LOAD_MP2_FW)
See #55758 (NDA) for additional bit definitions.

4
src/soc/amd/sabrina/Makefile.inc
View File

@ -97,10 +97,6 @@ ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y)
PSP_SOFTFUSE_BITS += 7
endif
ifeq ($(CONFIG_PSP_POSTCODES_ON_ESPI),y)
PSP_SOFTFUSE_BITS += 15
endif
ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y)
# Enable secure debug unlock
PSP_SOFTFUSE_BITS += 0