soc/intel/skylake: Generate ACPI DMAR table
If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the GFXVTBAR is only generated if the IGD is enabled. Change-Id: I8176401dd19aee7ad09a8a145b7a3801fe5b2ae1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
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@ -34,14 +34,17 @@
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/sgx.h>
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#include <intelblocks/uart.h>
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#include <intelblocks/systemagent.h>
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#include <soc/intel/common/acpi.h>
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#include <soc/acpi.h>
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#include <soc/cpu.h>
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#include <soc/iomap.h>
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#include <soc/msr.h>
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#include <soc/p2sb.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <soc/ramstage.h>
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#include <soc/systemagent.h>
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#include <string.h>
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#include <types.h>
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#include <vendorcode/google/chromeos/gnvs.h>
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@ -534,6 +537,74 @@ void generate_cpu_entries(device_t device)
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}
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}
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static unsigned long acpi_fill_dmar(unsigned long current)
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{
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struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD);
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const u32 gfx_vtbar = MCHBAR32(GFXVTBAR) & ~0xfff;
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const bool gfxvten = MCHBAR32(GFXVTBAR) & 1;
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/* iGFX has to be enabled, GFXVTBAR set and in 32-bit space. */
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if (igfx_dev && igfx_dev->enabled && gfxvten &&
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gfx_vtbar && !MCHBAR32(GFXVTBAR + 4)) {
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const unsigned long tmp = current;
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current += acpi_create_dmar_drhd(current, 0, 0, gfx_vtbar);
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current += acpi_create_dmar_drhd_ds_pci(current, 0, 2, 0);
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acpi_dmar_drhd_fixup(tmp, current);
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}
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struct device *const p2sb_dev = dev_find_slot(0, PCH_DEVFN_P2SB);
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const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff;
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const bool vtvc0en = MCHBAR32(VTVC0BAR) & 1;
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/* General VTBAR has to be set and in 32-bit space. */
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if (p2sb_dev && vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) {
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const unsigned long tmp = current;
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/* P2SB may already be hidden. There's no clear rule, when. */
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const u8 p2sb_hidden =
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pci_read_config8(p2sb_dev, PCH_P2SB_E0 + 1);
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pci_write_config8(p2sb_dev, PCH_P2SB_E0 + 1, 0);
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const u16 ibdf = pci_read_config16(p2sb_dev, PCH_P2SB_IBDF);
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const u16 hbdf = pci_read_config16(p2sb_dev, PCH_P2SB_HBDF);
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pci_write_config8(p2sb_dev, PCH_P2SB_E0 + 1, p2sb_hidden);
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current += acpi_create_dmar_drhd(current,
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DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
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current += acpi_create_dmar_drhd_ds_ioapic(current,
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2, ibdf >> 8, PCI_SLOT(ibdf), PCI_FUNC(ibdf));
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current += acpi_create_dmar_drhd_ds_msi_hpet(current,
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0, hbdf >> 8, PCI_SLOT(hbdf), PCI_FUNC(hbdf));
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acpi_dmar_drhd_fixup(tmp, current);
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}
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return current;
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}
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unsigned long northbridge_write_acpi_tables(struct device *const dev,
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unsigned long current,
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struct acpi_rsdp *const rsdp)
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{
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const struct soc_intel_skylake_config *const config = dev->chip_info;
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acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
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/* Create DMAR table only if we have VT-d capability. */
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if ((config && config->ignore_vtd) || !soc_is_vtd_capable())
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return current;
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printk(BIOS_DEBUG, "ACPI: * DMAR\n");
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acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar);
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current += dmar->header.length;
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current = acpi_align_current(current);
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acpi_add_table(rsdp, dmar);
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return current;
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}
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unsigned long acpi_madt_irq_overrides(unsigned long current)
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{
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int sci = acpi_sci_irq();
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@ -60,6 +60,7 @@ static struct device_operations pci_domain_ops = {
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.scan_bus = &pci_domain_scan_bus,
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.ops_pci_bus = &pci_bus_default_ops,
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#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
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.write_acpi_tables = &northbridge_write_acpi_tables,
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.acpi_name = &soc_acpi_name,
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#endif
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};
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@ -32,5 +32,7 @@ void acpi_mainboard_gnvs(global_nvs_t *gnvs);
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void southbridge_inject_dsdt(device_t device);
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unsigned long southbridge_write_acpi_tables(device_t device,
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unsigned long current, struct acpi_rsdp *rsdp);
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unsigned long northbridge_write_acpi_tables(struct device *,
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unsigned long current, struct acpi_rsdp *);
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#endif /* _SOC_ACPI_H_ */
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@ -19,6 +19,9 @@
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#define HPTC_OFFSET 0x60
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#define HPTC_ADDR_ENABLE_BIT (1 << 7)
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#define PCH_P2SB_IBDF 0x6c
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#define PCH_P2SB_HBDF 0x70
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#define PCH_P2SB_EPMASK0 0xB0
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#define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + ((mask_number) * 4))
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