skylake: Fix unwanted disablement of ACPI UPWE

In PORTSC, Port Enabled/Disabled(PED) is RW1CS.

When there is a USB device attached on system, current UPWE method
will set 1 to PED, this will cause port disabled as it's RW1CS.

This change is inspired by xhci_port_state_to_neutral in linux driver.
It will mask all RO and RWS bits and set WDE and WCE.

BUG=b:70777816
TEST=System won't be awakend from s3 automatically when usb devices
     is attached. Also system can be awakend by hotplugging usb
     devices under S3.

Change-Id: Ifd4c2d6640fea538e0ac71d7c5e73ab529e94f42
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/23848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Kane Chen 2018-02-23 10:11:27 +08:00 committed by Martin Roth
parent e099b30964
commit c3892c8fa8
1 changed files with 12 additions and 6 deletions

View File

@ -29,14 +29,20 @@ Method (UPWE, 3, Serialized)
/* Map ((XMEM << 16) + Local0 in PSCR */ /* Map ((XMEM << 16) + Local0 in PSCR */
OperationRegion (PSCR, SystemMemory, OperationRegion (PSCR, SystemMemory,
Add (ShiftLeft (Arg2, 16), Local0), 0x10) Add (ShiftLeft (Arg2, 16), Local0), 0x10)
Field (PSCR, AnyAcc, NoLock, Preserve) Field (PSCR, DWordAcc, NoLock, Preserve)
{ {
, 25, PSCT, 32,
UPCE, 1,
UPDE, 1,
} }
Store (One, UPCE) Store(PSCT, Local0)
Store (One, UPDE) /*
* And port status/control reg with RO and RWS bits
* RO bits: 0, 2:3, 10:13, 24, 28:30
* RWS bits: 5:9, 14:16, 25:27
*/
And (Local0, ~0x80FE0012, Local0)
/* Set WCE and WDE bits */
Or (Local0, 0x6000000, Local0)
Store(Local0, PSCT)
} }
/* /*