tegra124: Enable PWM clock, and set up PWM1 pin
Configure pin H1 for PWM1, and enable the PWM clock. BUG=none TEST=emerge-nyan chromeos-coreboot-nyan Original-Change-Id: I2f91ebd4666bd227686c08cedf3c1aa7abbe8215 Original-Signed-off-by: Andrew Chew <achew@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/185770 Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> (cherry picked from commit 069636d9299f64dd64466d45d2297593b37df4f2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic41515842fb883f44f228c77b4cd266e16124d99 Reviewed-on: http://review.coreboot.org/7400 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
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@ -201,6 +201,10 @@ static void setup_pinmux(void)
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PINMUX_DAP2_FS_FUNC_I2S1 | PINMUX_INPUT_ENABLE);
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pinmux_set_config(PINMUX_DAP2_SCLK_INDEX,
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PINMUX_DAP2_SCLK_FUNC_I2S1 | PINMUX_INPUT_ENABLE);
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/* PWM1 */
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pinmux_set_config(PINMUX_GPIO_PH1_INDEX,
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PINMUX_GPIO_PH1_FUNC_PWM1 | PINMUX_PULL_NONE);
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}
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static void setup_kernel_info(void)
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@ -250,7 +254,7 @@ static void mainboard_init(device_t dev)
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clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 | CLK_L_SDMMC4 |
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CLK_L_I2S0 | CLK_L_I2S1 | CLK_L_I2S2 |
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CLK_L_SPDIF | CLK_L_USBD | CLK_L_DISP1 |
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CLK_L_HOST1X,
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CLK_L_HOST1X | CLK_L_PWM,
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CLK_H_I2C2 | CLK_H_SBC1 | CLK_H_PMC |
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CLK_H_USB3,
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