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soc/intel/alderlake: Drop unused HECI_DISABLE_USING_SMM Kconfig

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Earlier generation platform used `HeciEnabled` chip config (set to 0)
and HECI_DISABLE_USING_SMM Kconfig to make the CSE function disable at
the end of the post. `HeciEnabled` chip config remains enabled in all
latest generation platforms hence drop HECI_DISABLE_USING_SMM Kconfig
selection from SoC Kconfig as CSE remains default enabled.

BUG=b:200644229
TEST=No functional impact during boot as CSE (B:0, D:0x16, F:0) device
is listed with `lspci`.

Change-Id: I5278e5c2e015b91bb3df3a3c73a6c659a56794b5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
This commit is contained in:
Subrata Banik 2021-09-21 19:35:40 +05:30
parent 4ca7b26346
commit c38d927899
1 changed files with 0 additions and 1 deletions
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src/soc/intel/alderlake/Kconfig
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@ -86,7 +86,6 @@ config CPU_SPECIFIC_OPTIONS
select UDELAY_TSC
select UDK_202005_BINDING
select DISPLAY_FSP_VERSION_INFO
select HECI_DISABLE_USING_SMM
config ALDERLAKE_CAR_ENHANCED_NEM
bool