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mb/google/guybrush/bootblock: add comment to PM_ACPI_CONF write 

Document what setting the PM_ACPI_S5_LPC_PIN_MODE and
PM_ACPI_S5_LPC_PIN_MODE_SEL bits causes. The corresponding code will
eventually be factored out and moved to the Cezanne SoC code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I10e3eee5cfc1c5ba2c88b8b7e83e96e481f787e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held 2021-09-30 20:46:15 +02:00 committed by Felix Held
parent 0cd81c325c
commit c3a9e53714
1 changed files with 1 additions and 0 deletions
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src/mainboard/google/guybrush/bootblock.c
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@ -61,6 +61,7 @@ void bootblock_mainboard_early_init(void)
dword |= PM_ESPI_CS_USE_DATA2; dword |= PM_ESPI_CS_USE_DATA2;
pm_write32(PM_SPI_PAD_PU_PD, dword); pm_write32(PM_SPI_PAD_PU_PD, dword);
/* Switch the pads that can be used as either LPC or secondary eSPI to 1.8V mode */
dword = pm_read32(PM_ACPI_CONF); dword = pm_read32(PM_ACPI_CONF);
dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL;
pm_write32(PM_ACPI_CONF, dword); pm_write32(PM_ACPI_CONF, dword);