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mb/google/dedede: Disable dynamic clock gating for cr50's GPIO 

Disable dynamic clock gating for the community cr50's IRQ lives on.
That IRQ is pulsed very quickly, and with clock gating enabled pulses
tend to be missed. This is expecially true on the default 0.0.22
firmware that cr50 comes with out of the factory.

BUG=b:154178408 b:154293730
BRANCH=None
TEST=build waddledoo successful and Linux has no TPM IRQ timeout error.

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I2b1b3ee59ebf6adce0653e7550b457e02d3c87df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Ian Feng 2020-04-17 16:45:08 +08:00 committed by Patrick Georgi
parent da38715ec3
commit c423293d20
1 changed files with 8 additions and 0 deletions
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8
src/mainboard/google/dedede/variants/baseboard/devicetree.cb
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@ -118,6 +118,14 @@ chip soc/intel/jasperlake
# Select eDP for port A
register "DdiPortAConfig" = "1"
# Disable PM to allow for shorter irq pulses
register "gpio_override_pm" = "1"
register "gpio_pm[0]" = "0"
register "gpio_pm[1]" = "0"
register "gpio_pm[2]" = "0"
register "gpio_pm[3]" = "0"
register "gpio_pm[4]" = "0"
# Enable HPD for DDI ports B/C
register "DdiPortBHpd" = "1"
register "DdiPortCHpd" = "1"