drivers/i2c/tpm: Work around missing board_cfg in Ti50 FW under 0.15
Ti50 FW under 0.15 is not support board cfg command which causes I2C errors and entering recovery mode. And ODM stocks are 0.12 pre-flashed. Add workaround for the old Ti50 chip. BUG=b:224650720 TEST=no I2C errors in coreboot. [ERROR] cr50_i2c_read: Address write failed [INFO ] .I2C stop bit not received Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ieec7842ca66b4c690df04a400cebcf45138c745d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
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@ -24,6 +24,15 @@ config MAINBOARD_HAS_I2C_TPM_GENERIC
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help
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Board has a generic I2C TPM support
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config MAINBOARD_NEEDS_I2C_TI50_WORKAROUND
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bool
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default n
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help
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Ti50 FW versions below 0.15 don't support the firmware_version or board_cfg registers,
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and trying to access them causes I2C errors. This config will skip accesses to these
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registers, and should be selected for boards using Ti50 chips with FW < 0.15. The config
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will be removed once all Ti50 stocks are updated to 0.15 or higher.
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config DRIVER_TIS_DEFAULT
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bool
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depends on I2C_TPM
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@ -500,7 +500,9 @@ int tpm_vendor_init(struct tpm_chip *chip, unsigned int bus, uint32_t dev_addr)
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printk(BIOS_DEBUG, "cr50 TPM 2.0 (i2c %u:0x%02x id 0x%x)\n",
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bus, dev_addr, did_vid >> 16);
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if (tpm_first_access_this_boot()) {
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/* Ti50 FW version under 0.15 doesn't support board cfg command
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TODO: remove this flag after all stocks Ti50 uprev to 0.15 or above */
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if (!CONFIG(MAINBOARD_NEEDS_I2C_TI50_WORKAROUND) && tpm_first_access_this_boot()) {
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/* This is called for the side-effect of printing the version string. */
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cr50_get_firmware_version(&ver);
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cr50_set_board_cfg();
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@ -60,6 +60,7 @@ config BOARD_GOOGLE_BASEBOARD_NISSA
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def_bool n
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select BOARD_GOOGLE_BRYA_COMMON
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select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
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select MAINBOARD_NEEDS_I2C_TI50_WORKAROUND
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select MEMORY_SOLDERDOWN
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select SOC_INTEL_ALDERLAKE_PCH_N
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select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW
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