Documentation: Advertise support for OpenSBI
Change-Id: Ie990bb95fcdcfab0246e8c694704022d9b8b5195 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Xiang Wang <merle@hardenedlinux.org>
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@ -23,8 +23,20 @@ On entry to a stage or payload (including SELF payloads),
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## Additional payload handoff requirements
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The location of cbmem should be placed in a node in the FDT.
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## OpenSBI
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In case the payload doesn't install it's own SBI, like the [RISCV-PK] does,
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[OpenSBI] can be used instead.
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It's loaded into RAM after coreboot has finished loading the payload.
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coreboot then will jump to OpenSBI providing a pointer to the real payload,
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which OpenSBI will jump to once the SBI is installed.
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Besides providing SBI it also sets protected memory regions and provides
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a platform independent console.
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The OpenSBI code is always run in M mode.
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## Trap delegation
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Traps are delegated in the ramstage.
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Traps are delegated to the payload.
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## SMP within a stage
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At the beginning of each stage, all harts save 0 are spinning in a loop on
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@ -44,3 +56,6 @@ The hart blocks until fn is non-null, and then calls it. If fn returns, we
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will panic if possible, but behavior is largely undefined.
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Only hart 0 runs through most of the code in each stage.
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[RISCV-PK]: https://github.com/riscv/riscv-pk
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[OpenSBI]: https://github.com/riscv/opensbi
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@ -17,7 +17,6 @@ The following things are still missing from this coreboot port:
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- Provide serial number to payload (e.g. in device tree)
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- Implement instruction emulation
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- Support for booting Linux on RISC-V
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- Add support to run OpenSBI payload in m-mode
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- SMP support in trap handler
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## Configuration
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