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soc/amd/picasso: introduce and use chipset device tree 

The chipset devicetree only has the essential PCIe devices enabled that
are needed for the SoC code to work. It also defines aliases for all
PCIe devices that can be used to reference the devices in the mainboard-
specific devicetrees and devicetree overrides. To make the change easier
to review that part will be done in a follow-up patch.

Despite missing in the PPR, device pci 18.7 exists on Picasso.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b7c3fd32579a23539594672593a243172c161c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held 2021-02-13 02:36:02 +01:00
parent db4b21a1d0
commit c4eb45fa85
8 changed files with 50 additions and 94 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/mainboard/amd/bilby/devicetree.cb
View File

@ -138,18 +138,12 @@ chip soc/amd/picasso
register "pspp_policy" = "DXIO_PSPP_BALANCED" register "pspp_policy" = "DXIO_PSPP_BALANCED"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on device domain 0 on
subsystemid 0x1022 0x1510 inherit subsystemid 0x1022 0x1510 inherit
device pci 0.0 on end # Root Complex
device pci 0.2 on end # IOMMU device pci 0.2 on end # IOMMU
device pci 1.0 on end # Dummy Host Bridge
device pci 1.1 on end # GPP Bridge 0 device pci 1.1 on end # GPP Bridge 0
device pci 1.2 on end # GPP Bridge 1 device pci 1.2 on end # GPP Bridge 1
device pci 1.5 on end # NVMe device pci 1.5 on end # NVMe
device pci 8.0 on end # Dummy Host Bridge
device pci 8.1 on # Bridge to Bus A device pci 8.1 on # Bridge to Bus A
device pci 0.0 on end # Internal GPU device pci 0.0 on end # Internal GPU
device pci 0.1 on end # Display HDA device pci 0.1 on end # Display HDA
@ -165,20 +159,10 @@ chip soc/amd/picasso
device pci 0.1 off end # integrated Ethernet MAC device pci 0.1 off end # integrated Ethernet MAC
device pci 0.2 off end # integrated Ethernet MAC device pci 0.2 off end # integrated Ethernet MAC
end end
device pci 14.0 on end # SMBus
device pci 14.3 on # D14F3 bridge device pci 14.3 on # D14F3 bridge
chip superio/smsc/sio1036 # optional debug card chip superio/smsc/sio1036 # optional debug card
end end
end end
device pci 14.6 off end # SDHCI
device pci 18.0 on end # Data fabric [0-7]
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
device pci 18.4 on end
device pci 18.5 on end
device pci 18.6 on end
device pci 18.7 on end
end # domain end # domain
device mmio 0xfedc9000 on end # UART0 device mmio 0xfedc9000 on end # UART0

16
src/mainboard/amd/mandolin/variants/cereme/devicetree.cb
View File

@ -138,16 +138,10 @@ chip soc/amd/picasso
register "pspp_policy" = "DXIO_PSPP_BALANCED" register "pspp_policy" = "DXIO_PSPP_BALANCED"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on device domain 0 on
subsystemid 0x1022 0x1510 inherit subsystemid 0x1022 0x1510 inherit
device pci 0.0 on end # Root Complex
device pci 0.2 on end # IOMMU device pci 0.2 on end # IOMMU
device pci 1.0 on end # Dummy Host Bridge
device pci 1.1 on end # Bridge to PCIe Ethernet chip device pci 1.1 on end # Bridge to PCIe Ethernet chip
device pci 8.0 on end # Dummy Host Bridge
device pci 8.1 on # Bridge to Bus A device pci 8.1 on # Bridge to Bus A
device pci 0.0 on end # Internal GPU device pci 0.0 on end # Internal GPU
device pci 0.1 on end # Display HDA device pci 0.1 on end # Display HDA
@ -163,20 +157,10 @@ chip soc/amd/picasso
device pci 0.1 off end # integrated Ethernet MAC device pci 0.1 off end # integrated Ethernet MAC
device pci 0.2 off end # integrated Ethernet MAC device pci 0.2 off end # integrated Ethernet MAC
end end
device pci 14.0 on end # SMBus
device pci 14.3 on # D14F3 bridge device pci 14.3 on # D14F3 bridge
chip superio/smsc/sio1036 # optional debug card chip superio/smsc/sio1036 # optional debug card
end end
end end
device pci 14.6 off end # SDHCI
device pci 18.0 on end # Data fabric [0-7]
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
device pci 18.4 on end
device pci 18.5 on end
device pci 18.6 on end
device pci 18.7 on end
end # domain end # domain
device mmio 0xfedc9000 on end # UART0 device mmio 0xfedc9000 on end # UART0

16
src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb
View File

@ -138,16 +138,10 @@ chip soc/amd/picasso
register "pspp_policy" = "DXIO_PSPP_BALANCED" register "pspp_policy" = "DXIO_PSPP_BALANCED"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on device domain 0 on
subsystemid 0x1022 0x1510 inherit subsystemid 0x1022 0x1510 inherit
device pci 0.0 on end # Root Complex
device pci 0.2 on end # IOMMU device pci 0.2 on end # IOMMU
device pci 1.0 on end # Dummy Host Bridge
device pci 1.3 on end # Bridge to PCIe Ethernet chip device pci 1.3 on end # Bridge to PCIe Ethernet chip
device pci 8.0 on end # Dummy Host Bridge
device pci 8.1 on # Bridge to Bus A device pci 8.1 on # Bridge to Bus A
device pci 0.0 on end # Internal GPU device pci 0.0 on end # Internal GPU
device pci 0.1 on end # Display HDA device pci 0.1 on end # Display HDA
@ -163,20 +157,10 @@ chip soc/amd/picasso
device pci 0.1 off end # integrated Ethernet MAC device pci 0.1 off end # integrated Ethernet MAC
device pci 0.2 off end # integrated Ethernet MAC device pci 0.2 off end # integrated Ethernet MAC
end end
device pci 14.0 on end # SMBus
device pci 14.3 on # D14F3 bridge device pci 14.3 on # D14F3 bridge
chip superio/smsc/sio1036 # optional debug card chip superio/smsc/sio1036 # optional debug card
end end
end end
device pci 14.6 off end # SDHCI
device pci 18.0 on end # Data fabric [0-7]
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
device pci 18.4 on end
device pci 18.5 on end
device pci 18.6 on end
device pci 18.7 on end
end # domain end # domain
device mmio 0xfedc9000 on end # UART0 device mmio 0xfedc9000 on end # UART0

21
src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
View File

@ -252,17 +252,10 @@ chip soc/amd/picasso
register "pspp_policy" = "DXIO_PSPP_POWERSAVE" register "pspp_policy" = "DXIO_PSPP_POWERSAVE"
device cpu_cluster 0 on
device lapic 0 on end
end
# See AMD 55570-B1 Table 13: PCI Device ID Assignments. # See AMD 55570-B1 Table 13: PCI Device ID Assignments.
device domain 0 on device domain 0 on
subsystemid 0x1022 0x1510 inherit subsystemid 0x1022 0x1510 inherit
device pci 0.0 on end # Root Complex
device pci 0.2 on end # IOMMU device pci 0.2 on end # IOMMU
device pci 1.0 on end # Dummy Host Bridge, must be enabled
device pci 1.1 off end # GPP Bridge 0
device pci 1.2 on # GPP Bridge 1 - Wifi device pci 1.2 on # GPP Bridge 1 - Wifi
chip drivers/wifi/generic chip drivers/wifi/generic
register "wake" = "GEVENT_8" register "wake" = "GEVENT_8"
@ -270,9 +263,6 @@ chip soc/amd/picasso
end end
end end
device pci 1.3 on end # GPP Bridge 2 - SD device pci 1.3 on end # GPP Bridge 2 - SD
device pci 1.4 off end # GPP Bridge 3
device pci 1.5 off end # GPP Bridge 4
device pci 8.0 on end # Dummy Host Bridge, must be enabled
device pci 8.1 on # Internal GPP Bridge 0 to Bus A device pci 8.1 on # Internal GPP Bridge 0 to Bus A
device pci 0.0 on end # Internal GPU device pci 0.0 on end # Internal GPU
device pci 0.1 on end # Display HDA device pci 0.1 on end # Display HDA
@ -363,10 +353,6 @@ chip soc/amd/picasso
device pci 0.6 off end # HDA device pci 0.6 off end # HDA
device pci 0.7 on end # non-Sensor Fusion Hub device device pci 0.7 on end # non-Sensor Fusion Hub device
end end
device pci 8.2 off # Internal GPP Bridge 0 to Bus B
device pci 0.0 off end # AHCI
end
device pci 14.0 on end # SM
device pci 14.3 on # - D14F3 bridge device pci 14.3 on # - D14F3 bridge
chip ec/google/chromeec chip ec/google/chromeec
device pnp 0c09.0 on device pnp 0c09.0 on
@ -398,13 +384,6 @@ chip soc/amd/picasso
end end
end end
end end
device pci 18.0 on end # Data fabric [0-7]
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
device pci 18.4 on end
device pci 18.5 on end
device pci 18.6 on end
end # domain end # domain
device mmio 0xfedc5000 on device mmio 0xfedc5000 on

23
src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
View File

@ -245,17 +245,10 @@ chip soc/amd/picasso
register "pspp_policy" = "DXIO_PSPP_POWERSAVE" register "pspp_policy" = "DXIO_PSPP_POWERSAVE"
device cpu_cluster 0 on
device lapic 0 on end
end
# See AMD 55570-B1 Table 13: PCI Device ID Assignments. # See AMD 55570-B1 Table 13: PCI Device ID Assignments.
device domain 0 on device domain 0 on
subsystemid 0x1022 0x1510 inherit subsystemid 0x1022 0x1510 inherit
device pci 0.0 on end # Root Complex
device pci 0.2 on end # IOMMU device pci 0.2 on end # IOMMU
device pci 1.0 on end # Dummy Host Bridge, must be enabled
device pci 1.1 off end # GPP Bridge 0
device pci 1.2 on # GPP Bridge 1 - Wifi device pci 1.2 on # GPP Bridge 1 - Wifi
chip drivers/wifi/generic chip drivers/wifi/generic
register "wake" = "GEVENT_8" register "wake" = "GEVENT_8"
@ -263,11 +256,7 @@ chip soc/amd/picasso
end end
end end
device pci 1.3 on end # GPP Bridge 2 - SD device pci 1.3 on end # GPP Bridge 2 - SD
device pci 1.4 off end # GPP Bridge 3
device pci 1.5 off end # GPP Bridge 4
device pci 1.6 off end # GPP Bridge 5
device pci 1.7 on end # GPP Bridge 6 - NVME device pci 1.7 on end # GPP Bridge 6 - NVME
device pci 8.0 on end # Dummy Host Bridge, must be enabled
device pci 8.1 on # Internal GPP Bridge 0 to Bus A device pci 8.1 on # Internal GPP Bridge 0 to Bus A
device pci 0.0 on end # Internal GPU device pci 0.0 on end # Internal GPU
device pci 0.1 on end # Display HDA device pci 0.1 on end # Display HDA
@ -385,10 +374,6 @@ chip soc/amd/picasso
device pci 0.6 off end # HDA device pci 0.6 off end # HDA
device pci 0.7 on end # non-Sensor Fusion Hub device device pci 0.7 on end # non-Sensor Fusion Hub device
end end
device pci 8.2 off # Internal GPP Bridge 0 to Bus B
device pci 0.0 off end # AHCI
end
device pci 14.0 on end # SM
device pci 14.3 on # - D14F3 bridge device pci 14.3 on # - D14F3 bridge
chip ec/google/chromeec chip ec/google/chromeec
device pnp 0c09.0 on device pnp 0c09.0 on
@ -434,14 +419,6 @@ chip soc/amd/picasso
end end
end end
end end
device pci 14.6 off end # Non-Functional SDHCI
device pci 18.0 on end # Data fabric [0-7]
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
device pci 18.4 on end
device pci 18.5 on end
device pci 18.6 on end
end # domain end # domain
chip drivers/generic/max98357a chip drivers/generic/max98357a

4
src/soc/amd/picasso/Kconfig
View File

@ -71,6 +71,10 @@ config CPU_SPECIFIC_OPTIONS
config SOC_AMD_COMMON_BLOCK_UCODE_SIZE config SOC_AMD_COMMON_BLOCK_UCODE_SIZE
default 3200 default 3200
config CHIPSET_DEVICETREE
string
default "soc/amd/picasso/chipset.cb"
config FSP_M_FILE config FSP_M_FILE
string "FSP-M (memory init) binary path and filename" string "FSP-M (memory init) binary path and filename"
depends on ADD_FSP_BINARIES depends on ADD_FSP_BINARIES

46
src/soc/amd/picasso/chipset.cb Normal file
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@ -0,0 +1,46 @@
# SPDX-License-Identifier: GPL-2.0-only
chip soc/amd/picasso
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 alias gnb on end
device pci 00.2 alias iommu off end
device pci 01.0 on end # Dummy Host Bridge, do not disable
device pci 01.1 alias gpp_bridge_0 off end
device pci 01.2 alias gpp_bridge_1 off end
device pci 01.3 alias gpp_bridge_2 off end
device pci 01.4 alias gpp_bridge_3 off end
device pci 01.5 alias gpp_bridge_4 off end
device pci 01.6 alias gpp_bridge_5 off end
device pci 01.7 alias gpp_bridge_6 off end
device pci 08.0 on end # Dummy Host Bridge, do not disable
device pci 08.1 alias internal_bridge_a off # internal bridge to bus A
device pci 0.0 alias gfx off end # internal GPU
device pci 0.1 alias gfx_hda off end # display HD Audio controller
device pci 0.2 alias crypto off end # cryptography coprocessor
device pci 0.3 alias xhci_0 off end
device pci 0.4 alias xhci_1 off end
device pci 0.5 alias acp off end # audio co-processor
device pci 0.6 alias hda off end # main HD Audio Controller
device pci 0.7 alias mp2 off end # sensor fusion hub (MP2)
end
device pci 08.2 alias internal_bridge_b off # internal bridge to bus B
device pci 0.0 alias sata off end
device pci 0.1 alias xgbe_0 off end
device pci 0.2 alias xgbe_1 off end
end
device pci 14.0 alias smbus on end # primary FCH function
device pci 14.3 alias lpc_bridge on end
device pci 14.6 alias sdhci off end
device pci 18.0 alias data_fabric_0 on end
device pci 18.1 alias data_fabric_1 on end
device pci 18.2 alias data_fabric_2 on end
device pci 18.3 alias data_fabric_3 on end
device pci 18.4 alias data_fabric_4 on end
device pci 18.5 alias data_fabric_5 on end
device pci 18.6 alias data_fabric_6 on end
device pci 18.7 alias data_fabric_7 on end
end
end

2
util/mainboard/google/trembyle/template/overridetree.cb
View File

@ -37,9 +37,7 @@ chip soc/amd/picasso
# See AMD 55570-B1 Table 13: PCI Device ID Assignments. # See AMD 55570-B1 Table 13: PCI Device ID Assignments.
device domain 0 on device domain 0 on
subsystemid 0x1022 0x1510 inherit subsystemid 0x1022 0x1510 inherit
device pci 1.6 off end # GPP Bridge 5
device pci 1.7 on end # GPP Bridge 6 - NVME device pci 1.7 on end # GPP Bridge 6 - NVME
device pci 14.6 off end # Non-Functional SDHCI
end # domain end # domain
device mmio 0xfedc4000 on end device mmio 0xfedc4000 on end