soc/amd/picasso: introduce and use chipset device tree
The chipset devicetree only has the essential PCIe devices enabled that are needed for the SoC code to work. It also defines aliases for all PCIe devices that can be used to reference the devices in the mainboard- specific devicetrees and devicetree overrides. To make the change easier to review that part will be done in a follow-up patch. Despite missing in the PPR, device pci 18.7 exists on Picasso. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b7c3fd32579a23539594672593a243172c161c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held
parent
db4b21a1d0
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c4eb45fa85
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@ -138,18 +138,12 @@ chip soc/amd/picasso
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register "pspp_policy" = "DXIO_PSPP_BALANCED"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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subsystemid 0x1022 0x1510 inherit
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device pci 0.0 on end # Root Complex
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device pci 0.2 on end # IOMMU
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device pci 1.0 on end # Dummy Host Bridge
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device pci 1.1 on end # GPP Bridge 0
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device pci 1.2 on end # GPP Bridge 1
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device pci 1.5 on end # NVMe
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device pci 8.0 on end # Dummy Host Bridge
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device pci 8.1 on # Bridge to Bus A
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device pci 0.0 on end # Internal GPU
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device pci 0.1 on end # Display HDA
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@ -165,20 +159,10 @@ chip soc/amd/picasso
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device pci 0.1 off end # integrated Ethernet MAC
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device pci 0.2 off end # integrated Ethernet MAC
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end
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device pci 14.0 on end # SMBus
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device pci 14.3 on # D14F3 bridge
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chip superio/smsc/sio1036 # optional debug card
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end
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end
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device pci 14.6 off end # SDHCI
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device pci 18.0 on end # Data fabric [0-7]
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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device pci 18.4 on end
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device pci 18.5 on end
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device pci 18.6 on end
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device pci 18.7 on end
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end # domain
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device mmio 0xfedc9000 on end # UART0
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@ -138,16 +138,10 @@ chip soc/amd/picasso
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register "pspp_policy" = "DXIO_PSPP_BALANCED"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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subsystemid 0x1022 0x1510 inherit
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device pci 0.0 on end # Root Complex
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device pci 0.2 on end # IOMMU
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device pci 1.0 on end # Dummy Host Bridge
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device pci 1.1 on end # Bridge to PCIe Ethernet chip
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device pci 8.0 on end # Dummy Host Bridge
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device pci 8.1 on # Bridge to Bus A
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device pci 0.0 on end # Internal GPU
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device pci 0.1 on end # Display HDA
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@ -163,20 +157,10 @@ chip soc/amd/picasso
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device pci 0.1 off end # integrated Ethernet MAC
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device pci 0.2 off end # integrated Ethernet MAC
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end
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device pci 14.0 on end # SMBus
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device pci 14.3 on # D14F3 bridge
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chip superio/smsc/sio1036 # optional debug card
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end
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end
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device pci 14.6 off end # SDHCI
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device pci 18.0 on end # Data fabric [0-7]
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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device pci 18.4 on end
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device pci 18.5 on end
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device pci 18.6 on end
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device pci 18.7 on end
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end # domain
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device mmio 0xfedc9000 on end # UART0
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@ -138,16 +138,10 @@ chip soc/amd/picasso
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register "pspp_policy" = "DXIO_PSPP_BALANCED"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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subsystemid 0x1022 0x1510 inherit
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device pci 0.0 on end # Root Complex
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device pci 0.2 on end # IOMMU
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device pci 1.0 on end # Dummy Host Bridge
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device pci 1.3 on end # Bridge to PCIe Ethernet chip
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device pci 8.0 on end # Dummy Host Bridge
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device pci 8.1 on # Bridge to Bus A
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device pci 0.0 on end # Internal GPU
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device pci 0.1 on end # Display HDA
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@ -163,20 +157,10 @@ chip soc/amd/picasso
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device pci 0.1 off end # integrated Ethernet MAC
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device pci 0.2 off end # integrated Ethernet MAC
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end
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device pci 14.0 on end # SMBus
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device pci 14.3 on # D14F3 bridge
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chip superio/smsc/sio1036 # optional debug card
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end
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end
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device pci 14.6 off end # SDHCI
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device pci 18.0 on end # Data fabric [0-7]
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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device pci 18.4 on end
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device pci 18.5 on end
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device pci 18.6 on end
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device pci 18.7 on end
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end # domain
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device mmio 0xfedc9000 on end # UART0
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@ -252,17 +252,10 @@ chip soc/amd/picasso
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register "pspp_policy" = "DXIO_PSPP_POWERSAVE"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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# See AMD 55570-B1 Table 13: PCI Device ID Assignments.
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device domain 0 on
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subsystemid 0x1022 0x1510 inherit
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device pci 0.0 on end # Root Complex
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device pci 0.2 on end # IOMMU
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device pci 1.0 on end # Dummy Host Bridge, must be enabled
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device pci 1.1 off end # GPP Bridge 0
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device pci 1.2 on # GPP Bridge 1 - Wifi
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chip drivers/wifi/generic
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register "wake" = "GEVENT_8"
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@ -270,9 +263,6 @@ chip soc/amd/picasso
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end
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end
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device pci 1.3 on end # GPP Bridge 2 - SD
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device pci 1.4 off end # GPP Bridge 3
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device pci 1.5 off end # GPP Bridge 4
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device pci 8.0 on end # Dummy Host Bridge, must be enabled
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device pci 8.1 on # Internal GPP Bridge 0 to Bus A
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device pci 0.0 on end # Internal GPU
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device pci 0.1 on end # Display HDA
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@ -363,10 +353,6 @@ chip soc/amd/picasso
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device pci 0.6 off end # HDA
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device pci 0.7 on end # non-Sensor Fusion Hub device
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end
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device pci 8.2 off # Internal GPP Bridge 0 to Bus B
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device pci 0.0 off end # AHCI
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end
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device pci 14.0 on end # SM
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device pci 14.3 on # - D14F3 bridge
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chip ec/google/chromeec
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device pnp 0c09.0 on
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@ -398,13 +384,6 @@ chip soc/amd/picasso
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end
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end
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end
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device pci 18.0 on end # Data fabric [0-7]
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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device pci 18.4 on end
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device pci 18.5 on end
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device pci 18.6 on end
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end # domain
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device mmio 0xfedc5000 on
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@ -245,17 +245,10 @@ chip soc/amd/picasso
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register "pspp_policy" = "DXIO_PSPP_POWERSAVE"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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# See AMD 55570-B1 Table 13: PCI Device ID Assignments.
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device domain 0 on
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subsystemid 0x1022 0x1510 inherit
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device pci 0.0 on end # Root Complex
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device pci 0.2 on end # IOMMU
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device pci 1.0 on end # Dummy Host Bridge, must be enabled
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device pci 1.1 off end # GPP Bridge 0
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device pci 1.2 on # GPP Bridge 1 - Wifi
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chip drivers/wifi/generic
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register "wake" = "GEVENT_8"
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@ -263,11 +256,7 @@ chip soc/amd/picasso
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end
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end
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device pci 1.3 on end # GPP Bridge 2 - SD
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device pci 1.4 off end # GPP Bridge 3
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device pci 1.5 off end # GPP Bridge 4
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device pci 1.6 off end # GPP Bridge 5
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device pci 1.7 on end # GPP Bridge 6 - NVME
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device pci 8.0 on end # Dummy Host Bridge, must be enabled
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device pci 8.1 on # Internal GPP Bridge 0 to Bus A
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device pci 0.0 on end # Internal GPU
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device pci 0.1 on end # Display HDA
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@ -385,10 +374,6 @@ chip soc/amd/picasso
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device pci 0.6 off end # HDA
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device pci 0.7 on end # non-Sensor Fusion Hub device
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end
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device pci 8.2 off # Internal GPP Bridge 0 to Bus B
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device pci 0.0 off end # AHCI
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end
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device pci 14.0 on end # SM
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device pci 14.3 on # - D14F3 bridge
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chip ec/google/chromeec
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device pnp 0c09.0 on
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@ -434,14 +419,6 @@ chip soc/amd/picasso
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end
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end
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end
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device pci 14.6 off end # Non-Functional SDHCI
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device pci 18.0 on end # Data fabric [0-7]
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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device pci 18.4 on end
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device pci 18.5 on end
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device pci 18.6 on end
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end # domain
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chip drivers/generic/max98357a
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@ -71,6 +71,10 @@ config CPU_SPECIFIC_OPTIONS
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config SOC_AMD_COMMON_BLOCK_UCODE_SIZE
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default 3200
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config CHIPSET_DEVICETREE
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string
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default "soc/amd/picasso/chipset.cb"
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config FSP_M_FILE
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string "FSP-M (memory init) binary path and filename"
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depends on ADD_FSP_BINARIES
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@ -0,0 +1,46 @@
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# SPDX-License-Identifier: GPL-2.0-only
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chip soc/amd/picasso
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 alias gnb on end
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device pci 00.2 alias iommu off end
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device pci 01.0 on end # Dummy Host Bridge, do not disable
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device pci 01.1 alias gpp_bridge_0 off end
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device pci 01.2 alias gpp_bridge_1 off end
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device pci 01.3 alias gpp_bridge_2 off end
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device pci 01.4 alias gpp_bridge_3 off end
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device pci 01.5 alias gpp_bridge_4 off end
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device pci 01.6 alias gpp_bridge_5 off end
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device pci 01.7 alias gpp_bridge_6 off end
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device pci 08.0 on end # Dummy Host Bridge, do not disable
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device pci 08.1 alias internal_bridge_a off # internal bridge to bus A
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device pci 0.0 alias gfx off end # internal GPU
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device pci 0.1 alias gfx_hda off end # display HD Audio controller
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device pci 0.2 alias crypto off end # cryptography coprocessor
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device pci 0.3 alias xhci_0 off end
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device pci 0.4 alias xhci_1 off end
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device pci 0.5 alias acp off end # audio co-processor
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device pci 0.6 alias hda off end # main HD Audio Controller
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device pci 0.7 alias mp2 off end # sensor fusion hub (MP2)
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end
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device pci 08.2 alias internal_bridge_b off # internal bridge to bus B
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device pci 0.0 alias sata off end
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device pci 0.1 alias xgbe_0 off end
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device pci 0.2 alias xgbe_1 off end
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end
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device pci 14.0 alias smbus on end # primary FCH function
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device pci 14.3 alias lpc_bridge on end
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device pci 14.6 alias sdhci off end
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device pci 18.0 alias data_fabric_0 on end
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device pci 18.1 alias data_fabric_1 on end
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device pci 18.2 alias data_fabric_2 on end
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device pci 18.3 alias data_fabric_3 on end
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device pci 18.4 alias data_fabric_4 on end
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device pci 18.5 alias data_fabric_5 on end
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device pci 18.6 alias data_fabric_6 on end
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device pci 18.7 alias data_fabric_7 on end
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end
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end
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@ -37,9 +37,7 @@ chip soc/amd/picasso
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# See AMD 55570-B1 Table 13: PCI Device ID Assignments.
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device domain 0 on
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subsystemid 0x1022 0x1510 inherit
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device pci 1.6 off end # GPP Bridge 5
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device pci 1.7 on end # GPP Bridge 6 - NVME
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device pci 14.6 off end # Non-Functional SDHCI
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end # domain
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device mmio 0xfedc4000 on end
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