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northbridge/amd: Modify 00670F00 chip.h to match DCT 

The Stoney device supports only a single channel of DRAM with
two DIMMs.  Correct the dimmensions of the SPD lookup array.

Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: <marcj303@gmail.com>
(cherry picked from commit 54a5e4a7092b77cca90894e86387f719fa3aa2c8)

Change-Id: Ib776133e411d483bb5b7e3c070199befc631d209
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17145
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Marshall Dawson 2016-10-08 09:12:27 -06:00 committed by Martin Roth
parent ade7800ec6
commit c56a558c18
1 changed files with 2 additions and 1 deletions
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3
src/northbridge/amd/pi/00670F00/chip.h
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@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
* Copyright (C) 2016 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -18,7 +19,7 @@
struct northbridge_amd_pi_00670F00_config
{
u8 spdAddrLookup[2][2][4];
u8 spdAddrLookup[1][1][2];
};
#endif