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AGESA,binaryPI: Remove redundant SSE enable 

Change-Id: Ib3bf731b74cb20e886d3ecd483b37b1e3fc64ebf
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37349
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michał Żygowski 2019-11-24 16:32:05 +01:00 committed by Kyösti Mälkki
parent 9b71804e4f
commit c574947223
1 changed files with 0 additions and 10 deletions
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10
src/drivers/amd/agesa/cache_as_ram.S
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@ -22,7 +22,6 @@
*/
#include "gcccar.inc"
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
.code32
@ -35,15 +34,6 @@ _cache_as_ram_setup:
post_code(0xa0)
/* enable SSE2 128bit instructions */
/* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
movl %cr4, %eax
orl $(3 << 9), %eax
movl %eax, %cr4
post_code(0xa1)
AMD_ENABLE_STACK
/* Align the stack. */