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exynos5250: Correct DDR3 Phy-reset value names. 

The name "LPDDR3PHY_CTRL_PHY_RESET_OFF" is not appropriate because the real
phy-reset is a low-active pin, so "off(0)" will trigger "start to reset".

To prevent confusion, we should rename the constants to "RESET_ENABLE" and
"RESET_DISABLE".

Change-Id: Iccba5ef3a2e992f877dea90741f0308c161758c9
Reviewed-on: https://gerrit.chromium.org/gerrit/61081
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/4357
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Hung-Te Lin 2013-07-08 18:41:02 +08:00 committed by Stefan Reinauer
parent 356833d0b5
commit c5aac958ae
2 changed files with 4 additions and 4 deletions
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4
src/cpu/samsung/exynos5250/dmc_init_ddr3.c
View File

@ -33,8 +33,8 @@ static void reset_phy_ctrl(void)
{
struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
writel(LPDDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl);
writel(LPDDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl);
writel(LPDDR3PHY_CTRL_PHY_RESET_ENABLE, &clk->lpddr3phy_ctrl);
writel(LPDDR3PHY_CTRL_PHY_RESET_DISABLE, &clk->lpddr3phy_ctrl);
#if 0
/*

4
src/cpu/samsung/exynos5250/setup.h
View File

@ -624,8 +624,8 @@ struct exynos5_phy_control;
*/
#define DECPROTXSET 0xFF
#define LPDDR3PHY_CTRL_PHY_RESET (1 << 0)
#define LPDDR3PHY_CTRL_PHY_RESET_OFF (0 << 0)
#define LPDDR3PHY_CTRL_PHY_RESET_DISABLE (1 << 0)
#define LPDDR3PHY_CTRL_PHY_RESET_ENABLE (0 << 0 )
#define PHY_CON0_RESET_VAL 0x17020a40
#define P0_CMD_EN (1 << 14)